參數(shù)資料
型號(hào)： DC571A
廠商： Linear Technology
文件頁(yè)數(shù)： 14/48頁(yè)
文件大小： 0K
描述： BOARD DELTA SIGMA ADC LTC2418
軟件下載： QuikEval System
設(shè)計(jì)資源： DC571A Design File
DC571A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 7.5
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
工作溫度： 0°C ~ 70°C
已用 IC / 零件： LTC2418
已供物品： 板
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LTC2414/LTC2418
21
241418fa
Figure 7. External Serial Clock, CS = 0 Operation
External Serial Clock, 3-Wire I/O
This timing mode utilizes a 3-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal, see Figure 7. CS
may be permanently tied to ground, simplifying the user
interface or isolation barrier.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
typically 1ms after VCC exceeds approximately 2V. The
level applied to SCK at this time determines if SCK is
internal or external. SCK must be driven LOW prior to the
end of POR in order to enter the external serial clock timing
mode.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is
ready. EOC = 1 while the conversion is in progress and
EOC = 0 once the conversion ends. On the falling edge of
EOC, the conversion result is loaded into an internal static
shift register. The input data is then shifted in via the SDI
pin on the rising edge of SCK (including the first rising
edge) and the output data is shifted out of the SDO pin on
each falling edge of SCK. EOC can be latched on the first
rising edge of SCK. On the 32nd falling edge of SCK, SDO
goes HIGH (EOC = 1) indicating a new conversion has
begun.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 8.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
APPLICATIO S I FOR ATIO
WU
UU
(1)
(0)
EN
SGL
A2
A1
A0
ODD/
SIGN
SDI
DON’T CARE
EOC
BIT 31
SDO
SCK
(EXTERNAL)
CS
MSB
SIG
BIT 0
PARITY
LSB
BIT 6
BIT 27
BIT 26
BIT 25
BIT 24
BIT 28
BIT 29
BIT 30
DATA OUTPUT
CONVERSION
241418 F07
CONVERSION
VCC
FO
REF+
REF–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
919
11
12
21
28
1
8
10
18
17
15
16
20
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
VCC
1
F
2.7V TO 5.5V
LTC2414/
LTC2418
3-WIRE
SPI INTERFACE
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