參數(shù)資料
型號(hào)： DC571A
廠商： Linear Technology
文件頁(yè)數(shù)： 9/48頁(yè)
文件大小： 0K
描述： BOARD DELTA SIGMA ADC LTC2418
軟件下載： QuikEval System
設(shè)計(jì)資源： DC571A Design File
DC571A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 7.5
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
工作溫度： 0°C ~ 70°C
已用 IC / 零件： LTC2418
已供物品： 板
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LTC2414/LTC2418
17
241418fa
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2414/
LTC2418 can operate with an external conversion clock.
The converter automatically detects the presence of an
external clock signal at the FO pin and turns off the internal
oscillator. The frequency fEOSC of the external signal must
be at least 2560Hz (1Hz notch frequency) to be detected.
The external clock signal duty cycle is not significant as
long as the minimum and maximum specifications for the
high and low periods tHEO and tLEO are observed.
While operating with an external conversion clock of a
frequency fEOSC, the converter provides better than 110dB
normal mode rejection in a frequency range fEOSC/2560
±4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from fEOSC/2560
is shown in Figure 4.
Whenever an external clock is not present at the FO pin, the
converter automatically activates its internal oscillator and
enters the Internal Conversion Clock mode. The converter
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external
serial clock. If the change occurs during the conversion
state, the result of the conversion in progress may be
outside specifications but the following conversions will
not be affected. If the change occurs during the data output
state and the converter is in the Internal SCK mode, the
serial clock duty cycle may be affected but the serial data
stream will remain valid.
Table 5 summarizes the duration of each state and the
achievable output data rate as a function of FO.
SERIAL INTERFACE PINS
The LTC2414/LTC2418 transmit the conversion results
and receive the start of conversion command through a
synchronous 4-wire interface. During the conversion and
sleep states, this interface can be used to assess the con-
verter status and during the data I/O state it is used to read
the conversion result and write in channel selection bits.
Figure 4. LTC2414/LTC2418 Normal Mode Rejection
When Using an External Oscillator of Frequency fEOSC
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY fEOSC/2560(%)
–12
–8
–4
048
12
NORMAL
MODE
REJECTION
(dB)
241418 F04
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
APPLICATIO S I FOR ATIO
WU
UU
Table 4. LTC2414/LTC2418 Output Data Format
Differential Input Voltage
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
…
Bit 6
VIN*
EOC
DMY
SIG
MSB
LSB
VIN* ≥ 0.5 VREF**
0
0110
0
…
0
0.5 VREF** – 1LSB
0
0101
1
…
1
0.25 VREF**
0
0101
0
…
0
0.25 VREF** – 1LSB
0
0100
1
…
1
0
0100
0
…
0
–1LSB
0
0011
1
…
1
– 0.25 VREF**
0
0011
0
…
0
– 0.25 VREF** – 1LSB
0
0010
1
…
1
– 0.5 VREF**
0
0010
0
…
0
VIN* < –0.5 VREF**
0
0001
1
…
1
*The differential input voltage VIN = IN
+ – IN–.
**The differential reference voltage VREF = REF+ – REF–.
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