參數(shù)資料
型號： DC742A
廠商： Linear Technology
文件頁數(shù)： 11/28頁
文件大?。?/td> 0K
描述： BOARD DELTA SIGMA ADC LTC2449
軟件下載： QuikEval System
設(shè)計資源： DC742A Design File
DC742A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 8k
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
已用 IC / 零件： LTC2449
已供物品： 板
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LTC2444/LTC2445/
LTC2448/LTC2449
19
2444589fb
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 7.
In order to select the internal serial clock timing mode, the
EXT pin must be tied HIGH.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state. Alternatively,
BUSY (Pin 2) may be used to monitor the status of the
conversion in progress. BUSY is HIGH during the conver-
Figure 7. Internal Serial Clock, Single Cycle Operation
MSB
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
BIT 20 BIT 19
BIT 0
LSB
Hi-Z
2444 F08
SIG
BIT 29
“0”
BIT 30
EOC
Hi-Z
CS
SCK
SDI
SDO
BUSY
BIT 31
1
0
EN
SGL
A2
A1
A0
OSR3
OSR2
OSR1
OSR0
TWOX
ODD
12345
6
7
89
10
11
12
13
14
32
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
TEST EOC
DON'T CARE
<tEOC(TEST)
VCC
FO
REF+
REF–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28
35
29
30
8
15
16
23
7
38
37
1,4,5,6,31,32,33,39
36
34
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
2
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
1
F
4.5V TO 5.5V
LTC2448
4-WIRE
SPI INTERFACE
BUSY
sion and goes LOW at the conclusion. It remains LOW until
the result is read from the device.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CS remains LOW. In order to prevent the device
from exiting the low power sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time tEOCtest after the falling edge of CS
(if EOC = 0) or tEOCtest after EOC goes LOW (if CS is LOW
during the falling edge of EOC). The value of tEOCtest is
500ns. If CS is pulled HIGH before time tEOCtest, the device
remains in the sleep state. The conversion result is held in
the internal static shift register.
APPLICATIO S I FOR ATIO
WU
UU
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