參數(shù)資料
型號(hào)： DC742A
廠商： Linear Technology
文件頁(yè)數(shù)： 14/28頁(yè)
文件大小： 0K
描述： BOARD DELTA SIGMA ADC LTC2449
軟件下載： QuikEval System
設(shè)計(jì)資源： DC742A Design File
DC742A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 8k
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
已用 IC / 零件： LTC2449
已供物品： 板
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LTC2444/LTC2445/
LTC2448/LTC2449
21
2444589fb
APPLICATIO S I FOR ATIO
WU
U
Figure 9. Internal Serial Clock, Continuous Operation
CS
SCK
SDI
SDO
BUSY
2444 F10
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
MSB
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
BIT 20 BIT 19
BIT 0
LSB
SIG
BIT 29
“0”
BIT 30
EOC
BIT 31
1
0
EN
SGL
A2
A1
A0
OSR3
OSR2
OSR1
OSR0
TWOX
ODD
12345
6
7
89
10
11
12
13
14
32
DON'T CARE
VCC
FO
REF+
REF–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28
35
29
30
8
15
16
23
7
38
37
1,4,5,6,31,32,33,39
36
34
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
2
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
1
F
4.5V TO 5.5V
LTC2448
4-WIRE
SPI INTERFACE
BUSY
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 9. CS may be permanently tied to ground, simplify-
ing the user interface or isolation barrier. The internal
serial clock mode is selected by tying EXT HIGH.
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1) and BUSY = 1. Once the
conversion is complete, SCK, BUSY and SDO go LOW
(EOC = 0) indicating the conversion has finished and the
device has entered the low power sleep state. The part
remains in the sleep state a minimum amount of time
(
≈500ns) then immediately begins outputting data. The
data output cycle begins on the first rising edge of SCK and
ends after the 32nd rising edge. Data is shifted out the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
used to shift the conversion result into external circuitry.
EOC can be latched on the first rising edge of SCK and the
last bit of the conversion result can be latched on the 32nd
rising edge of SCK. After the 32nd rising edge, SDO goes
HIGH (EOC = 1) indicating a new conversion is in progress.
SCK remains HIGH during the conversion.
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