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參數(shù)資料
| 型號(hào)： | DC742A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 16/28頁 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2449 |
| 軟件下載： | QuikEval System |
| 設(shè)計(jì)資源： | DC742A Design File DC742A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuikEval™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 8k |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 已用 IC / 零件： | LTC2449 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC2449CUHF#PBF-ND - IC ADC 24BIT 38-QFN LTC2449IUHF#PBF-ND - IC ADC 24BIT HI SPEED 38QFN LTC2449IUHF#TRPBF-ND - IC ADC 24BIT HI SPEED 38QFN LTC2449CUHF#TRPBF-ND - IC ADC 24BIT HI SPEED 38QFN LTC2449IUHF-ND - IC ADC 24BIT HI SPEED 38QFN LTC2449CUHF-ND - IC ADC 24BIT HI SPEED 38QFN LTC2449CUHF#TR-ND - IC ADC 24BIT HI SPEED 38QFN LTC2449IUHF#TR-ND - IC ADC 24BIT HI SPEED 38QFN |
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LTC2444/LTC2445/
LTC2448/LTC2449
23
2444589fb
clock applied to FO. Combining a large OSR with a reduced
sample rate leads to notch frequencies fN near DC while
maintaining simple antialiasing requirements. A 100kHz
clock applied to FO results in a NULL at 0.6Hz plus all
harmonics up to 20kHz, see Figure 13. This is useful in
applications requiring digitalization of the DC component
of a noisy input signal and eliminates the need of placing
a 0.6Hz filter in front of the ADC.
An external oscillator operating from 100kHz to 20MHz
can be implemented using the LTC1799 (resistor set
SOT-23 oscillator), see Figure 16. By floating pin 4 (DIV)
of the LTC1799, the output oscillator frequency is:
f
MHz
k
R
OSC
SET
=
10
The normal mode rejection characteristic shown in
Figure 13 is achieved by applying the output of the LTC1799
(with RSET = 100k) to the FO pin on the LTC2444/LTC2445/
LTC2448/LTC2449 with SDI tied HIGH (OSR = 32768).
Figure 13. LTC2444/LTC2445/LTC2448/LTC2449 Normal
Mode Rejection (External Oscillator at 90kHz)
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
–40
–20
0
8
2440 F14
–60
–80
246
10
–100
–120
–140
NORMAL
MODE
REJECTION
(dB)
Figure 12. LTC2444/LTC2445/LTC2448/LTC2449
Normal Mode Rejection (Internal Oscillator)
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
–60
–40
0
1440 F13
–80
–100
1000000
2000000
–120
1.8MHz
–140
–20
NORMAL
MODE
REJECTION
(dB)
REJECTION > 120dB
If FO is grounded, fS is set by the on-chip oscillator at
1.8MHz
±5% (over supply and temperature variations). At
an OSR of 32,768, the first NULL is at fN = 55Hz and the no
latency output rate is fN/8 = 6.9Hz. At the maximum OSR,
the noise performance of the device is 280nVRMS(LTC2444/
LTC2448) and 200nVRMS (LTC2445/LTC2449) with better
than 80dB rejection of 50Hz
±2%and60Hz±2%.Sincethe
OSR is large (32,768) the wide band rejection is extremely
large and the antialiasing requirements are simple. The
first multiple of fS occurs at 55Hz 32,768 = 1.8MHz, see
Figure 12.
The first NULL becomes fN = 7.04kHz with an OSR of 256
(an output rate of 880Hz) and FO grounded. While the
NULL has shifted, the sample rate remains constant. As a
result of constant modulator sampling rate, the linearity,
offset and full-scale performance remains unchanged as
does the first multiple of fS.
The sample rate fS and NULL fN, may also be adjusted by
driving the FO pin with an external oscillator. The sample
rate is fS = fEOSC/5, where fEOSC is the frequency of the
APPLICATIO S I FOR ATIO
WU
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