參數(shù)資料
型號(hào)： DC746A
廠商： Linear Technology
文件頁(yè)數(shù)： 13/36頁(yè)
文件大?。?/td> 0K
描述： BOARD DELTA SIGMA ADC LTC2412
軟件下載： QuikEval System
設(shè)計(jì)資源： DC746A Design File
DC746A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 7.5
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
工作溫度： 0°C ~ 70°C
已用 IC / 零件： LTC2412
已供物品： 板
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LTC2412CGN#TR-ND - IC CONV A/D 24B 2CH DIFF 16-SSOP
LTC2412IGN-ND - IC CONV A/D 24B 2CH DIFF 16-SSOP
LTC2412CGN-ND - IC ADC 2CH DIFF-IN 24BIT 16SSOP
LTC2412
20
2412f
APPLICATIO S I FOR ATIO
WU
U
device returns to the sleep state and the conversion result
is held in the internal static shift register.
If CS remains LOW longer than tEOCtest, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle concludes
after the 32nd rising edge. Data is shifted out the SDO pin
on each falling edge of SCK. The internally generated serial
clock is output to the SCK pin. This signal may be used to
shift the conversion result into external circuitry. EOC can
be latched on the first rising edge of SCK and the last bit
of the conversion result on the 32nd rising edge of SCK.
After the 32nd rising edge, SDO goes HIGH (EOC = 1), SCK
stays HIGH and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
of SCK, see Figure 9. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 32 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to
the SCK pin or by never pulling CS HIGH when SCK is LOW.
Whenever SCK is LOW, the LTC2412’s internal pull-up at
pin SCK is disabled. Normally, SCK is not externally driven
if the device is in the internal SCK timing mode. However,
certain applications may require an external driver on SCK.
If this driver goes Hi-Z after outputting a LOW signal, the
LTC2412’s internal pull-up remains disabled. Hence, SCK
remains LOW. On the next falling edge of CS, the device is
switched to the external SCK timing mode. By adding an
external 10k pull-up resistor to SCK, this pin goes HIGH
once the external driver goes Hi-Z. On the next CS falling
edge, the device will remain in the internal SCK timing
mode.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the
conversion status. If the device is in the sleep state (EOC
= 0), SCK will go LOW. Once CS goes HIGH (within the time
period defined above as tEOCtest), the internal pull-up is
activated. For a heavy capacitive load on the SCK pin, the
Figure 8. Internal Serial Clock, Single Cycle Operation
SDO
SCK
(INTERNAL)
CS
MSB
SIG
CH0/CH1
BIT 0
LSB24
BIT 5
TEST EOC
BIT 27
BIT 26
BIT 28
BIT 29
BIT 30
EOC
BIT 31
SLEEP
DATA OUTPUT
CONVERSION
2412 F08
<tEOCtest
VCC
10k
Hi-Z
TEST EOC
(OPTIONAL)
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
VCC
VCC
FO
REF+
SCK
CH1+
CH1–
SDO
GND
CS
114
2
3
13
6
7
12
8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO VCC
CH0+
CH0–
4
5
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1
F
2.7V TO 5.5V
LTC2412
3-WIRE
SPI INTERFACE
REF–
SLEEP
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