參數(shù)資料
型號(hào)： DC746A
廠商： Linear Technology
文件頁(yè)數(shù)： 14/36頁(yè)
文件大?。?/td> 0K
描述： BOARD DELTA SIGMA ADC LTC2412
軟件下載： QuikEval System
設(shè)計(jì)資源： DC746A Design File
DC746A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 7.5
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
工作溫度： 0°C ~ 70°C
已用 IC / 零件： LTC2412
已供物品： 板
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LTC2412IGN#PBF-ND - IC ADC 2CH DIFF-IN 24BIT 16SSOP
LTC2412IGN#TRPBF-ND - IC ADC 2CH DIFF-IN 24BIT 16SSOP
LTC2412CGN#TRPBF-ND - IC ADC 2CH DIFF-IN 24BIT 16SSOP
LTC2412CGN#PBF-ND - IC ADC 2CH DIFF-IN 24BIT 16SSOP
LTC2412IGN#TR-ND - IC CONV A/D 24B 2CH DIFF 16-SSOP
LTC2412CGN#TR-ND - IC CONV A/D 24B 2CH DIFF 16-SSOP
LTC2412IGN-ND - IC CONV A/D 24B 2CH DIFF 16-SSOP
LTC2412CGN-ND - IC ADC 2CH DIFF-IN 24BIT 16SSOP
LTC2412
21
2412f
APPLICATIO S I FOR ATIO
WU
U
internal pull-up may not be adequate to return SCK to a
HIGH level before CS goes low again. This is not a concern
under normal conditions where CS remains LOW after
detecting EOC = 0. This situation is easily overcome by
adding an external 10k pull-up resistor to the SCK pin.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 10. CS may be permanently tied to ground, simpli-
fying the user interface or isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after VCC exceeds 2V. An internal weak
pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
data output state. The data output cycle begins on the
first rising edge of SCK and ends after the 32nd rising
edge. Data is shifted out the SDO pin on each falling edge
of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result can be latched on the 32nd rising
edge of SCK. After the 32nd rising edge, SDO goes HIGH
(EOC = 1) indicating a new conversion is in progress. SCK
remains HIGH during the conversion.
Figure 9. Internal Serial Clock, Reduced Data Output Length
SDO
SCK
(INTERNAL)
CS
>tEOCtest
MSB
SIG
CH0/CH1
BIT 8
TEST EOC
BIT 27
BIT 26
BIT 28
BIT 29
BIT 30
EOC
BIT 31
EOC
BIT 0
DATA OUTPUT
Hi-Z
DATA
OUTPUT
CONVERSION
SLEEP
2412 F09
<tEOCtest
VCC
10k
TEST EOC
(OPTIONAL)
TEST EOC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
VCC
VCC
FO
REF+
SCK
CH1+
CH1–
SDO
GND
CS
114
2
3
13
6
7
12
8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO VCC
CH0+
CH0–
4
5
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1
F
2.7V TO 5.5V
LTC2412
3-WIRE
SPI INTERFACE
REF–
SLEEP
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