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參數(shù)資料
| 型號： | DC859A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 13/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR LTC4267 |
| 設(shè)計(jì)資源： | DC859A Design File DC859A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 電源管理，以太網(wǎng)供電（POE） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | LTC4267 |
| 已供物品： | 板 |
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LTC4267
20
4267fc
Choose resistance values for R1 and R2 to be as large as
possible to minimize any efciency loss due to the static
current drawn from VOUT, but just small enough so that
when VOUT is in regulation, the error caused by the nonzero
input current from the output of the resistor divider to the
error amplier pin is less than 1%.
Error Amplier and Optoisolator Considerations
In an isolated topology, the selection of the external error
amplier depends on the output voltage of the switching
regulator. Typical error ampliers include a voltage refer-
ence of either 1.25V or 2.5V. The output of the amplier
and the amplier upper supply rail are often tied together
internally. The supply rail is usually specied with a wide
upper voltage range, but it is not allowed to fall below the
reference voltage. This can be a problem in an isolated
switcher design if the amplier supply voltage is not prop-
erly managed. When the switcher load current decreases
and the output voltage rises, the error amplier responds
by pulling more current through the LED. The LED voltage
can be as large as 1.5V, and along with RLIM, reduces the
supply voltage to the error amplier. If the error amp does
not have enough headroom, the voltage drop across the
LED and RLIM may shut the amplier off momentarily,
causing a lock-up condition in the main loop. The switcher
will undershoot and not recover until the error amplier
releases its sink current. Care must be taken to select the
reference voltage and RLIM value so that the error amplier
always has enough headroom. An alternate solution that
avoids these problems is to utilize the LT1431 or LT4430
where the output of the error amplier and amplier supply
rail are brought out to separate pins.
The PD designer must also select an optoisolator such
that its bandwidth is sufciently wider than the bandwidth
of the main control loop. If this step is overlooked, the
main control loop may be difcult to stabilize. The output
collector resistor of the optoisolator can be selected for
an increase in bandwidth at the cost of a reduction in gain
of this stage.
Output Transformer Design Considerations
Since the external feedback resistor divider sets the
output voltage, the PD designer has relative freedom in
selecting the transformer turns ratio. The PD designer
can use simple ratios of small integers (i.e. 1:1, 2:1, 3:2)
which yields more freedom in setting the total turns and
mutual inductance and may allow the use of an off the
shelf transformer.
Transformer leakage inductance on either the primary or
secondary causes a voltage spike to occur after the output
switch (Q1 in Figure 11) turns off. The input supply volt-
age plus the secondary-to-primary referred voltage of the
yback pulse (including leakage spike) must not exceed
the allowed external MOSFET breakdown rating. This spike
is increasingly prominent at higher load currents, where
more stored energy must be dissipated. In some cases,
a “snubber” circuit will be required to avoid overvoltage
breakdown at the MOSFET’s drain node. Application
Note 19 is a good reference for snubber design.
Current Sense Resistor Consideration
The external current sense resistor (RSENSE in Figure 11)
allows the designer to optimize the current limit behavior
for a particular application. As the current sense resistor
is varied from several ohms down to tens of milliohms,
peak swing current goes from a fraction of an ampere to
several amperes. Care must be taken to ensure proper
circuit operation, especially for small current sense resis-
tor values.
Choose RSENSE such that the switching current exercises
the entire range of the ITH/RUNvoltage.Thenominalvoltage
range is 0.7V to 1.9V and RSENSE can be determined by
experiment. The main loop can be temporarily stabilized
by connecting a large capacitor on the power supply. Apply
the maximum load current allowable at the power sup-
ply output based on the class of the PD. Choose RSENSE
such that ITH/RUN approaches 1.9V. Finally, exercise the
output load current over the entire operating range and
ensure that ITH/RUN voltage remains within the 0.7V to
1.9V range. Layout is critical around the RSENSE resistor.
For example, a 0.020Ω sense resistor, with one milliohm
(0.001Ω) of parasitic resistance will cause a 5% reduction
in peak switch current. The resistance of printed circuit
copper traces cannot necessarily be ignored and good
layout techniques are mandatory.
APPLICATIO S I FOR ATIO
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