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參數(shù)資料
| 型號(hào)： | DC859A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR LTC4267 |
| 設(shè)計(jì)資源： | DC859A Design File DC859A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 電源管理，以太網(wǎng)供電（POE） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | LTC4267 |
| 已供物品： | 板 |
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LTC4267
13
4267fc
Figure 5. LTC4267 VPORTN Undervoltage Lockout
the classication current is reenabled. C1 will discharge
through the PD circuitry and the POUT pin will go to a high
impedance state.
limit because the load capacitor is charged with a current
below the IEEE inrush current limit specication.
As the LTC4267 switches from the low to high level current
limit, the current will increase momentarily. This current
spike is a result of the LTC4267 charging the last 1.5V at
the high level current limit. When charging a 10F capaci-
tor, the current spike is typically 100s wide and 125%
of the nominal low level current limit.
The LTC4267 stays in the high level current limit mode
until the input voltage drops below the UVLO turn-off
threshold. This dual level current limit provides the sys-
tem designer with the exibility to design PDs which are
compatible with legacy PSEs while also being able to take
advantage of the higher power allocation available in an
IEEE 802.3af system.
During the current limited turn on, a large amount of
power is dissipated in the power MOSFET. The LTC4267
PD interface is designed to accept this thermal load and
is thermally protected to avoid damage to the onboard
power MOSFET. Note that in order to adhere to the IEEE
802.3af standard, it is necessary for the PD designer to
ensure the PD steady state power consumption falls within
the limits shown in Table 2. In addition, the steady state
current must be less than ILIM_HI.
Power Good
The LTC4267 PD Interface includes a power good circuit
(Figure 6) that is used to indicate that load capacitor C1
is fully charged and that the switching regulator can start
operation. The power good circuit monitors the voltage
across the internal UVLO power MOSFET and PWRGD is
asserted when the voltage falls below 1.5V. The power
good circuit includes hysteresis to allow the LTC4267 to
operate near the current limit point without inadvertently
disabling PWRGD. The MOSFET voltage must increase to
3V before PWRGD is disabled.
If a sudden increase in voltage appears on the input line,
this voltage step will be transferred through capacitor C1
and appear across the power MOSFET. The response of
the LTC4267 will depend on the magnitude of the voltage
step, the rise time of the step, the value of capacitor C1
and the switching regulator load. For fast rising inputs,
APPLICATIO S I FOR ATIO
WU
UU
Input Current Limit
IEEE 802.3af species a maximum inrush current and also
species a minimum load capacitor between the VPORTP
and POUT pins. To control turn-on surge current in the
system, the LTC4267 integrates a dual level current limit
circuit with an onboard power MOSFET and sense resis-
tor to provide a complete inrush control circuit without
additional external components. At turn-on, the LTC4267
will limit the input current to the low level, allowing the
load capacitor to ramp up to the line voltage in a controlled
manner.
The LTC4267 has been specically designed to interface
with legacy PSEs which do not meet the inrush current
requirement of the IEEE 802.3af specication. At turn-on
the LTC4267 current limit is set to the lower level. After C1
is charged up and the POUT – VPORTN voltage difference is
below the power good threshold, the LTC4267 switches
to the high level current limit. The dual level current limit
allows legacy PSEs with limited current sourcing capability
to power up the PD while also allowing the PD to draw full
power from an IEEE 802.3af PSE. The dual level current
limit also allows use of arbitrarily large load capacitors.
The IEEE 802.3af specication mandates that at turn-on
the PD not exceed the inrush current limit for more than
50ms. The LTC4267 is not restricted to the 50ms time
C1
5F
MIN
VPORTN
VPORTP
POUT
PGND
LTC4267
4267 F05
TO
PSE
UNDERVOLTAGE
LOCKOUT
CIRCUIT
CURRENT-LIMITED
TURN ON
+
INPUT
LTC4267
VOLTAGE
POWER MOSFET
0V TO UVLO*
OFF
>UVLO*
ON
*UVLO INCLUDES HYSTERESIS
RISING INPUT THRESHOLD
–36V
FALLING INPUT THRESHOLD
–30.5V
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