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參數(shù)資料
| 型號(hào)： | DDC112U/1K |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 20-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | GREEN, PLASTIC, SOIC-28 |
| 文件頁(yè)數(shù)： | 17/34頁(yè) |
| 文件大小： | 776K |
| 代理商： | DDC112U/1K |
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DDC112
24
SBAS085B
www.ti.com
RETRIEVAL
BEFORE AND AFTER CONV
TOGGLES (CONTINUOUS MODE)
For the absolute maximum time for data retrieval, data can
be retrieved
before and after CONV toggles. Nearly all of TINT
is available for data retrieval. Figure 26 illustrates how this is
done by combining the two previous methods. You must
pause the retrieval during CONV toggling to prevent digital
noise, as discussed previously, and finish before the next
data is ready. The maximum number of DDC112s that can
be daisy-chained together is:
Ts
s
INT
DCLK
––
20
2
40
τ
For TINT = 500s and DCLK = 10MHz, the maximum number
of DDC112s is 119.
RETRIEVAL: NONCONTINUOUS MODE
Retrieving in noncontinuous mode is slightly different as
compared with the continuous mode. As shown in Figure 27
and described in detail in Application Bulletin SBAA024
(available for download at www.ti.com), DVALID goes LOW
in time t30 after the first integration completes. If TINT is
shorter than this time, all of t31 is available to retrieve data
before the other side’s data is ready. For TINT > t30, the first
integration’s data is ready before the second integration
completes. Data retrieval must be delayed until the second
integration completes leaving less time available for retrieval.
The time available is t31 – (TINT – t30). The second integration’s
data must be retrieved before the next round of integrations
begin. This time is highly dependent on the pattern used to
generate CONV. As with the continuous mode, data retrieval
must halt before and after CONV toggles (t28 and t29) and be
completed before new data is ready (t26).
POWER-UP SEQUENCING
Prior to power-up, all digital and analog input pins must be
LOW. At the time of power-up, these signal inputs can be
biased to a voltage other than 0V, however, they should
never exceed AVDD or DVDD. The level of CONV at power-
up is used to determine which side (A or B) will be integrated
first. Before integrations can begin though, CONV must
toggle; see Figure 28.
DCLK
DXMIT
DVALID
CONV
DOUT
Side B
Data
Side A
Data
T
INT
t
29
t
28
t
26
T
INT
T
INT
FIGURE 26. Readback
Before and After CONV Toggles.
CLK = 10MHz
CLK = 15MHz
SYMBOL
DESCRIPTION
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
t26
Hold Time for DXMIT HIGH Before Falling
2
1.33
s
Edge of DVALID
t28
Data Retrieval Shutdown Before Edge of CONV
10
s
t29
Data Retrieval Start-Up After dge of CONV
10
s
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| DDC112UG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual Current Input 20-Bit RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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| DDC112UK/1K | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual Current Input 20-Bit RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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