參數(shù)資料
型號(hào)： DDC112U/1K
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 2-CH 20-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28
封裝： GREEN, PLASTIC, SOIC-28
文件頁(yè)數(shù)： 18/34頁(yè)
文件大小： 776K
代理商： DDC112U/1K
DDC112
25
SBAS085B
www.ti.com
T
INT
T
INT
t
30
T
INT
T
INT
t
31
Side A
Data
Side B
Data
CONV
DVALID
DXMIT
DCLK
DOUT
FIGURE 27. Readback in Noncontinuous Mode.
FIGURE 28. Timing Diagram at Power-Up of the DDC112.
t
32
t
33
Integrate Side A
Integrate Side B
Power-Up
Initialization
Release State
Start
Integration
CONV
(HIGH at power-up)
CONV
(LOW at power-up)
Power Supplies
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t32
Power-On Initialization Period
50
s
t33
From Release Edge to Integration Start
50
s
TABLE XI. Timing for the DDC112 Power-Up Sequence.
CLK = 10MHz
CLK = 15MHz
SYMBOL
DESCRIPTION
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
t30
1st Ncont Mode Data Ready (see SBAA024)
421.1
±0.3
280.8
s
t31
2nd Ncont Mode Data Ready (see SBAA024)
454.8
303.2
s
LAYOUT
Power Supplies and Grounding
Both AVDD and DVDD should be as quiet as possible. It is
particularly important to eliminate noise from AVDD that is
non-synchronous with the DDC112 operation. Figure 29
illustrates two acceptable ways to supply power to the
DDC112. The first case shows two separate +5V supplies for
AVDD and DVDD. In this case, each +5V supply of the
DDC112 should be bypassed with 10
F solid tantalum ca-
pacitors and 0.1
F ceramic capacitors. The second case
shows the DVDD power supply derived from the AVDD supply
with a < 10
isolation resistor. In both cases, the 0.1F
capacitors should be placed as close to the DDC112 pack-
age as possible.
Shielding Analog Signal Paths
As with any precision circuit, careful printed circuit layout will
ensure the best performance. It is essential to make short,
direct interconnections and avoid stray wiring capacitance—
particularly at the analog input pins. Digital signals should be
kept as far from the analog input signals as possible on the
PC board.
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