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參數(shù)資料
| 型號： | DDC118IRTCR |
| 英文描述： | Octal Current Input 20-Bit Analog-To-Digital Converter |
| 中文描述： | 八路電流輸入20位模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 19/30頁 |
| 文件大?。?/td> | 384K |
| 代理商： | DDC118IRTCR |
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SBAS325A JUNE 2004 REVISED JUNE 2005
www.ti.com
19
Looking at the state diagram, one can see that the CONV
pattern needed to generate a given state progression is not
unique. Upon entering states 1 or 8, the DDC118 remains
in those states until mbsy goes low, independent of CONV.
As long as the m/r/az cycle is underway, the state machine
ignores CONV (see Figure 10, page 14). The top two
signals in Figure 16 are different CONV patterns that
produce the same state. This feature allows flexibility in
generating ncont mode CONV patterns. For example, the
DDC118 Evaluation Fixture operates in the ncont mode by
generating a square wave with pulse width < t
6
. Figure 17
illustrates operation in the ncont mode using a 50% duty
cycle CONV signal with T
INT
= 512 CLK periods. Care
must be exercised when using a square wave to generate
CONV. There are certain integration times that must be
avoided since they produce very short intervals for state 2
(or state 7 if CONV is inverted). As seen in the state
diagram, the state progresses from 2 to 3 as soon as
CONV is high. The state machine does not insure that the
duration of state 2 is long enough to properly prepare the
next side for integration (t
11
). This must be done by the
user with proper timing of CONV. For example, if CONV is
a square wave with T
INT
= 970 CLK periods, state 2 will
only be 9 CLK periods long; therefore, t
11
will not be met.
CONV1
CONV2
2
3
1
3
4
4
1
2
State
mbsy
Figure 16. Equivalent CONV Signals in Non-Continuous Mode
CONV
DVALID
2
3
1
3
4
4
1
State
Integration
Status
mbsy
Int B
Int A
Int B
Side A
Data
Side B
Data
Side A
Data
Int A
Figure 17. Non-Continuous Mode Timing with a 50% Duty Cycle CONV Signal
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DDC118IRTCT | Octal Current Input 20-Bit Analog-To-Digital Converter |
| DDG-GJS-K1 | LED GaP |
| DDR-GJS-J2L1-1-I1 | LED GaP |
| DDR-GJS-K1 | LED GaP |
| DDR-GJS-K2 | LED GaP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DDC118IRTCRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Octal Current-Input 20-Bit RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| DDC118IRTCT | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Octal Current-Input 20-Bit RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| DDC118IRTCT | 制造商:Texas Instruments 功能描述:IC ADC 20BIT OCTAL 48-VQFN |
| DDC118IRTCT | 制造商:Texas Instruments 功能描述:A/D CONVERTER (A-D) IC ((NW)) |
| DDC118IRTCTG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Octal Current-Input 20-Bit RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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