參數(shù)資料
型號: DDC118IRTCR
英文描述: Octal Current Input 20-Bit Analog-To-Digital Converter
中文描述: 八路電流輸入20位模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù): 23/30頁
文件大?。?/td> 384K
代理商: DDC118IRTCR
""#
SBAS325A JUNE 2004 REVISED JUNE 2005
www.ti.com
23
RETRIEVAL
BEFORE
CONV TOGGLES
(CONTINUOUS MODE)
Date retrieval before CONV toggles is the most
straightforward method. Data retrieval begins soon after
DVALID goes low and finishes before CONV toggles, as
shown in Figure 23. For best performance, data retrieval
must stop t
28
before CONV toggles. This method is most
appropriate for longer integration times. The maximum
time available for readback is T
INT
– t
27
– t
28
. For DCLK =
10MHz and CLK = 4MHz, the maximum number of
DDC118s that can be daisy-chained together (FORMAT =
high) is calculated by Equation 1:
T
INT
355.125 s
160
DCLK
NOTE: 128
τ
DCLK
is used for FORMAT = low.
where
τ
DCLK
is the period of the data clock. For example,
if T
INT
= 1000
μ
s and DCLK = 10MHz, the maximum
number of DDC118s (FORMAT = high) is shown in
Equation 2:
1000 s
355.125 s
(160)(100ns)
40.30
40DDC118s
(or 50 for FORMAT = low).
SYMBOL
DESCRIPTION
CLK = 4MHz, CLK_4X = 0
CLK = 4.8MHz, CLK_4X = 0
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
t27
t28
Cont Mode Data Ready
345.00
±
0.125
287.5
±
0.104
μ
s
Data Retrieval Shutdown Before Edge of CONV
10
10
μ
s
Figure 23. Readback
Before
CONV Toggles
(1)
(2)
Side B
Data
Side A
Data
T
INT
T
INT
t
27
t
28
CONV
DVALID
DCLK
DOUT
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