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參數(shù)資料
| 型號(hào)： | DDC118IRTCT |
| 英文描述： | Octal Current Input 20-Bit Analog-To-Digital Converter |
| 中文描述： | 八路電流輸入20位模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 25/30頁(yè) |
| 文件大小： | 384K |
| 代理商： | DDC118IRTCT |
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SBAS325A JUNE 2004 REVISED JUNE 2005
www.ti.com
25
RETRIEVAL
BEFORE
AND
AFTER
CONV
TOGGLES (CONTINUOUS MODE)
For the absolute maximum time for data retrieval, data can
be retrieved
before and after
CONV toggles. Nearly all of
T
INT
is available for data retrieval. Figure 25 illustrates
how this is done by combining the two previous methods.
Retrieval during CONV toggling to prevent digital noise, as
discussed previously, and finished before the next data is
ready. The maximum number of DDC118s that can be
daisy-chained together (FORMAT = high) is:
T
INT
20 s
160
DCLK
1.75 s
NOTE: 128
τ
DCLK
is used for FORMAT = low.
For T
INT
= 400
μ
s and DCLK = 10MHz, the maximum
number of DDC118s is 23 (or 29 for FORMAT = low).
RETRIEVAL: NONCONTINUOUS MODE
Retrieving in noncontinuous mode is slightly different,
compared to the continuous mode. As illustrated in
Figure 26, DVALID goes low in time t
30
after the first
integration completes. If T
INT
is shorter than this time, all
of t
31
is available to retrieve data before the other side data
is ready. For T
INT
> t
30
, the first integration data is ready
before the second integration completes. Data retrieval
must be delayed until the second integration completes,
leaving less time available for retrieval. The time available
is t
31
– (T
INT
– t
30
). The second integration’s data must be
retrieved before the next round of integration begins. This
time is highly dependent on the pattern used to generate
CONV. As with the continuous mode, data retrieval must
halt before and after CONV toggles (t
28
, t
29
) and be
completed before new data is ready (t
26
).
SYMBOL
DESCRIPTION
CLK = 4MHZ, CLK_4X = 0
MIN
TYP
1.75
10
10
CLK = 4.8MHZ, CLK_4X = 0
MIN
TYP
1.458
10
10
UNITS
MAX
MAX
t26
t28
t29
Hold Time that DOUT is Valid Before Falling Edge of DVALID
Data Retrieval Shutdown Before Edge of CONV
Data Retrieval Start-Up After Edge of CONV
μ
s
μ
s
μ
s
Figure 25. Readback
Before and After
CONV Toggles
SYMBOL
DESCRIPTION
CLK = 4MHz, CLK_4X = 0
MIN
TYP
344.75
±
0.25
362.500
CLK = 4.8MHz, CLK_4X = 0
MIN
TYP
287.292
±
0.208
302.083
UNITS
MAX
MAX
t30
t31
1st ncont Mode Data Ready
2nd ncont Mode Data Ready
μ
s
μ
s
Figure 26. Readback in Non-Continuous Mode
…
…
…
…
…
…
…
…
…
…
…
…
DCLK
DVALID
CONV
DOUT
Side B
Data
Side A
Data
T
INT
t
29
t
28
t
26
T
INT
T
INT
…
…
…
…
T
INT
T
INT
t
30
T
INT
T
INT
t
31
Side A
Data
Side B
Data
CONV
DVALID
DCLK
DOUT
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DDC118IRTCT | 制造商:Texas Instruments 功能描述:IC ADC 20BIT OCTAL 48-VQFN |
| DDC118IRTCT | 制造商:Texas Instruments 功能描述:A/D CONVERTER (A-D) IC ((NW)) |
| DDC118IRTCTG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Octal Current-Input 20-Bit RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| DDC11XEVM-PDK | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開(kāi)發(fā)工具 DDC11xEVM-PDK Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類(lèi)型:ADC 工具用于評(píng)估:ADS130E08 接口類(lèi)型:SPI 工作電源電壓:- 6 V to + 6 V |
| DDC122LH | 制造商:DIODES 制造商全稱(chēng):Diodes Incorporated 功能描述:NPN PRE-BIASED SMALL SIGNAL SOT-563 DUAL SURFACE MOUNT TRANSISTOR |
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