參數(shù)資料
型號(hào): DG536DN-E3
廠商: Vishay Siliconix
文件頁數(shù): 2/12頁
文件大小: 0K
描述: IC AMP/VIDEO/MUX LP 2CH 44PLCC
標(biāo)準(zhǔn)包裝: 300
功能: 視頻多路復(fù)用器
電路: 1 x 16:1
導(dǎo)通狀態(tài)電阻: 90 歐姆
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 7.5 V ~ 18 V
電流 - 電源: 5µA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 管件
www.vishay.com
10
Document Number: 70070
S-71241–Rev. E, 25-Jun-07
Vishay Siliconix
DG535/536
DETAILED DESCRIPTION
The DG535/536 are 16-channel single-ended multiplexers
with on-chip address logic and control latches.
The multiplexer connects one of sixteen inputs (S1, S2
through S16) to a common output (D) under the control of a
4-bit binary address (A0 to A3). The specific input channel
selected for each address is given in the Truth Table.
All four address inputs have on-chip data latches which are
controlled by the Strobe (ST) input. These latches are
transparent when Strobe is high but they maintain the
chosen address when Strobe goes low. To facilitate easy
microprocessor control in large matrices a choice of three
independent logic inputs (EN, CS and CS) are provided on
chip. These inputs are gated together (see Figure 11) and
only when EN = CS = 1 and CS = 0 can an output switch be
selected. This necessary logic condition is then latched-in
when Strobe (ST) goes low.
Break-before-make switching prevents momentary shorting
when changing from one input to another.
The devices feature a two-level switch arrangement whereby
two banks of eight switches (first level) are connected via two
series switches (second level) to a common DRAIN output.
In order to improve crosstalk all sixteen first level switches
are configured as “T” switches (see Figure 12).
With this method SW2 operates out of phase with SW1 and
SW3. In the on condition SW1 and SW3 are closed with SW2
open whereas in the off condition SW1 and SW3 are open
and SW2 closed. In the off condition the input to SW3 is
effectively the isolation leakage of SW1 working into the
on-resistance of SW2 (typically 200 Ω).
The two second level series switches further improve
crosstalk and help to minimize output capacitance.
The DIS output can be used to signal external circuitry. DIS
is a high impedance to GND when no channel is selected
and a low impedance to GND when any one channel is
selected.
The DG535/536 have extensive applications where any high
frequency video or digital signals are switched or routed.
Exceptional
crosstalk
and
bandwidth
performance
is
achieved by using n-channel DMOS FETs for the “T” and
series switches.
It can clearly be seen from Figure 13 that there exists a PN
junction between the substrate and the drain/source
terminals.
Should a signal which is negative with respect to the
substrate (GND pin) be connected to a source or drain
terminal, then the PN junction will become forward biased
and current will flow between the signal source and GND.
This effective shorting of the signal source to GND will not
necessarily cause any damage to the device, provided that
the total current flowing is less than the maximum rating, (i.e.,
20 mA).
Figure 11. CS, CS, EN, ST Control Logic
Latch
CS
EN
ST
CS
A0
Latch
A1
Latch
A2
Latch
A3
Latch
Decode
Logic
Figure 12. “T” Switch Arrangement
Figure 13. Cross-Section of a Single
DMOS Switch
SW2
SW1
SW3
Signal
IN
Signal
OUT
Signal
GND
Source
Gate
Drain
p-
n+
p
Substrate
GND
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