參數(shù)資料
型號(hào): DM74ALS652
廠商: Fairchild Semiconductor Corporation
英文描述: Octal 3-STATE Bus Transceiver and Register(八總線(xiàn)收發(fā)器和寄存器(三態(tài)輸出))
中文描述: 八路三態(tài)總線(xiàn)收發(fā)器和寄存器(八總線(xiàn)收發(fā)器和寄存器(三態(tài)輸出))
文件頁(yè)數(shù): 2/6頁(yè)
文件大?。?/td> 57K
代理商: DM74ALS652
www.fairchildsemi.com
2
D
Function Table
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Don’t Care (Either LOW or HIGH Logic Levels, including transitions)
H/L
=
Either LOW or HIGH Logic Level excluding transitions
=
Positive-going edge of pulse
Note 1:
The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled,
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
Note 2:
Select control
=
L; clocks can occur simultaneously
Select control
=
H; clocks must be staggered in order to load both registers.
Logic Diagram
Inputs
Data I/O (Note 1)
Operation or Function
GAB
X
L
L
L
L
L
H
H
H
GBA
H
X
H
H
L
L
H
H
H
CAB
H/L
H/L
X
X
X
CBA
H/L
H/L
X
H/L
X
SAB
X
X
X
X
X
X
L
X
X
(Note 2)
X
SBA
X
X
X
X
L
H
X
X
X
A1 thru A8
Input
Not Specified
Input
Input
Output
Output
Input
Input
Input
B1 thru B8
Not Specified Store A, Hold B
Input
Store B, Hold A
Input
Store A and B Data
Input
Isolation, Hold Storage
Input
Real-Time B Data to A Bus
Input
Stored B Data to A Bus
Output
Real-Time A Data to B Bus
Output
Stored A Data to B Bus
Output
Store A in both Registers
L
L
X
(Note 2)
H
Output
Input
Store B in both Registers
H
L
H or L
H or L
H
Output
Output
Stored A Data to B Bus and
Stored B Data to A Bus
相關(guān)PDF資料
PDF描述
DM74ALS652NT 10-Bit Buffer/Driver With 3-State Outputs 24-SOIC -40 to 85
DM74ALS652WM Octal 3-STATE Bus Transceiver and Register
DM74ALS74A Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear(雙正邊緣觸發(fā)的D觸發(fā)器(帶預(yù)置和清除端))
DM74ALS74AN Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear
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