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參數(shù)資料
| 型號： | DM9000 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ISA TO ETHERNET MAC CONTROLLER WITH INTEGRATED 10/100 PHY |
| 中文描述： | ISA以以太網(wǎng)MAC控制器，它集成10/100網(wǎng)卡芯片 |
| 文件頁數(shù)： | 13/54頁 |
| 文件大小： | 575K |
| 代理商： | DM9000 |
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DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final
Version: DM9000-DS-F02
June 26, 2002
13
6.1 Network Control Register (00H)
Bit
Name
7
EXT_PHY
Default
0,RW
Description
Selects external PHY when set. Selects Internal PHY when clear. This bit will not
be affected after software reset
Wakeup Event Enable
When set, it enables the wakeup function. Clearing this bit will also clears all
wakeup event status
This bit will not be affected after a software reset
Reserved
Force Collision Mode, used for testing
Full-Duplex Mode. Read only on Internal PHY mode. R/W on External PHY mode
Loopback Mode
Bit 2 1
0 0 Normal
0 1 MAC Internal loopback
1 0 Internal PHY 100M mode digital loopback
1 1 (Reserved)
Software reset and auto clear after 10us
6
WAKEEN
0,RW
5
4
3
RESERVED
FCOL
FDX
LBK
0,RO
0,RW
0,RW
00,RW
2:1
0
RST
0,RW
6.2 Network Status Register (01H)
Bit
Name
7
SPEED
Default
0,RO
Description
Media Speed 0:100Mbps 1:10Mbps, when Internal PHY is used. This bit has no
meaning when LINKST=0
Link Status 0:link failed 1:link OK, when Internal PHY is used
Wakeup Event Status. Clears by read or write 1
This bit will not be affected after software reset
Reserved
TX Packet 2 Complete Status. Clears by read or write 1
Transmit completion of packet index 2
TX Packet 1 Complete status. Clears by read or write 1
Transmit completion of packet index 1
RX FIFO Overflow
Reserved
6
LINKST
0,RO
5
WAKEST
0,RW/C1
4
3
RESERVED
TX2END
0,RO
0,RW/C1
2
TX1END
0,RW/C1
1
0
RXOV
RESERVED
0,RO
0,RO
6.3 TX Control Register (02H)
Bit
Name
7
RESERVED
Default
0,RO
Description
Reserved
Transmit Jabber Disable
When set, the transmit Jabber Timer (2048 bytes) is disabled. Otherwise it is Enable
Excessive Collision Mode Control : 0:aborts this packet when excessive collision
counts more than 15, 1: still tries to transmit this packet
PAD Appends Disable for Packet Index 2
CRC Appends Disable for Packet Index 2
PAD Appends Disable for Packet Index 1
CRC Appends Disable for Packet Index 1
TX Request. Auto clears after sending completely
6
TJDIS
0,RW
5
EXCECM
0,RW
4
3
2
1
0
PAD_DIS2
CRC_DIS2
PAD_DIS1
CRC_DIS1
TXREQ
0,RW
0,RW
0,RW
0,RW
0,RW
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相關(guān)代理商/技術(shù)參數(shù) |
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| DM9000()EVB | 制造商:DAVICOM 功能描述:BOARD EVALUATION DM9000 制造商:DAVICOM 功能描述:DM9000, MAC CNTLR, ENET, EVAL BOARD 制造商:DAVICOM 功能描述:EVAL BOARD, DM9000, MAC CNTLR, ENET; ;ROHS COMPLIANT: YES |
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| DM9000A_06 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Ethernet Controller with General Processor Interface |
| DM9000AE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Ethernet Controller with General Processor Interface |
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