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參數(shù)資料
| 型號： | DM9000 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ISA TO ETHERNET MAC CONTROLLER WITH INTEGRATED 10/100 PHY |
| 中文描述： | ISA以以太網(wǎng)MAC控制器，它集成10/100網(wǎng)卡芯片 |
| 文件頁數(shù)： | 15/54頁 |
| 文件大?。?/td> | 575K |
| 代理商： | DM9000 |
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DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final
Version: DM9000-DS-F02
June 26, 2002
15
6.7 RX Status Register ( 06H )
Bit
Name
7
Default
0,RO
Description
RF
Runt Frame
It is set to indicate that the size of the received frame is smaller than 64 bytes
Multicast Frame
It is set to indicate that the received frame has a multicast address
Late Collision Seen
It is set to indicate that a late collision is found during the frame reception
Receive Watchdog Time-Out
It is set to indicate that it receives more than 2048 bytes
Physical Layer Error
It is set to indicate that a physical layer error is found during the frame reception
Alignment Error
It is set to indicate that the received frame ends with a non-byte boundary
CRC Error
It is set to indicate that the received frame ends with a CRC error
FIFO Overflow Error
It is set to indicate that a FIFO overflow error happens during the frame reception
6
MF
0,RO
5
LCS
0,RO
4
RWTO
0,RO
3
PLE
0,RO
2
AE
0,RO
1
CE
0,RO
0
FOE
0,RO
6.8 Receive Overflow Counter Register ( 07H )
Bit
Name
7
RXFU
Default
0,R/C
Description
Receive Overflow Counter Overflow
This bit is set when the ROC has an overflow condition
Receive Overflow Counter
This is a statistic counter to indicate the received packet count upon FIFO overflow
6:0
ROC
0,R/C
6.9 Back Pressure Threshold Register (08H)
Bit
Name
7:4
BPHW
Default
3H, RW
Description
Back Pressure High Water Overflow Threshold. MAC will generate the jam pattern
when RX SRAM free space is lower than this threshold value
Default is 3K-byte free space. Please do not exceed SRAM size
(1 unit=1K bytes)
Jam Pattern Time. Default is 200us
bit3 bit2 bit1 bit0 time
0 0 0 0 5us
0 0 0 1 10us
0 0 1 0 15us
0 0 1 1 25us
0 1 0 0 50us
0 1 0 1 100us
0 1 1 0 150us
0 1 1 1 200us
1 0 0 0 250us
1 0 0 1 300us
1 0 1 0 350us
1 0 1 1 400us
1 1 0 0 450us
1 1 0 1 500us
1 1 1 0 550us
1 1 1 1 600us
3:0
JPT
7H, RW
相關PDF資料 |
PDF描述 |
|---|---|
| DM9000E | ISA TO ETHERNET MAC CONTROLLER WITH INTEGRATED 10/100 PHY |
| DM9006CJ | Gate Expander |
| DM9006CN | Gate Expander |
| DM9009CJ | Dual 4-input NAND Gate |
| DM9009CN | Dual 4-input NAND Gate |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DM9000()EVB | 制造商:DAVICOM 功能描述:BOARD EVALUATION DM9000 制造商:DAVICOM 功能描述:DM9000, MAC CNTLR, ENET, EVAL BOARD 制造商:DAVICOM 功能描述:EVAL BOARD, DM9000, MAC CNTLR, ENET; ;ROHS COMPLIANT: YES |
| DM9000_09 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:ISA to Ethernet MAC Controller with Integrated 10/100 PHY |
| DM9000A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Ethernet Controller with General Processor Interface 臺灣Davicom公司出品的48pin、10/100M網(wǎng)絡控制芯片 |
| DM9000A_06 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Ethernet Controller with General Processor Interface |
| DM9000AE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Ethernet Controller with General Processor Interface |
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