參數(shù)資料
型號: DM9000
廠商: Electronic Theatre Controls, Inc.
英文描述: ISA TO ETHERNET MAC CONTROLLER WITH INTEGRATED 10/100 PHY
中文描述: ISA以以太網(wǎng)MAC控制器,它集成10/100網(wǎng)卡芯片
文件頁數(shù): 19/54頁
文件大小: 575K
代理商: DM9000
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final
Version: DM9000-DS-F02
June 26, 2002
19
6.22 Vendor ID Register (28H~29H)
Bit
Name
7:0
VIDH
7:0
VIDL
Default
0AH,RO
46H.RO
Description
Vendor ID High Byte (29H)
Vendor ID Low Byte (28H)
6.23 Product ID Register (2AH~2BH)
Bit
Name
7:0
PIDH
7:0
PIDL
Default
90H,RO
00H.RO
Description
Product ID High Byte (2BH)
Product ID Low Byte (2AH)
6.24 Chip Revision Register (2CH)
Bit
Name
7:0
CHIPR
Default
00H,RO
Description
CHIP Revision
6.25 Special Mode Control Register ( 2FH )
Bit
Name
7
SM_EN
6~3
RESERVED
2
FLC
1
FB1
0
FB0
Default
0,RW
0,RO
0,RW
0,RW
0,RW
Description
Special Mode Enable
Reserved
Force Late Collision
Force Longest Back-off time
Force Shortest Back-off time
6.26 Memory Data Read Command without Address Increment Register (F0H)
Bit
Name
Default
7:0
MRCMDX
X,RO
Read data from RX SRAM. After the read of this command, the read pointer of
internal SRAM is unchanged
Description
6.27 Memory Data Read Command with Address Increment Register (F2H)
Bit
Name
Default
7:0
MRCMD
X,RO
Read data from RX SRAM. After the read of this command, the read pointer is
increased by 1,2, or 4, depends on the operator mode (8-bit,16-bit and 32-bit
respectively)
Description
6.28 Memory Data Read_address Register (F4H~F5H)
Bit
Name
Default
7:0
MDRAH
00H,R/W
7:0
MDRAL
00H,R/W
Description
Memory Data Read_ address High Byte. It will be set to 0Ch, when IMR bit7 =1
Memory Data Read_ address Low Byte
6.29 Memory Data Write Command without Address Increment Register (F6H)
Bit
Name
Default
7:0
MWCMDX
X,WO
Write data to TX SRAM. After the write of this command, the write pointer is
unchanged
Description
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