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參數(shù)資料
| 型號(hào)： | DM9102D |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SINGLE CHIP FAST ETHEMET NIC CONTROLLER |
| 中文描述： | 單晶片快速以太網(wǎng)NIC控制器 |
| 文件頁(yè)數(shù)： | 27/70頁(yè) |
| 文件大?。?/td> | 2245K |
| 代理商： | DM9102D |
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Preliminary datasheet
Version: DM9102D-DS-P02
Jan. 14, 2005
27
4
IAFM
0,RO
Inverse Address Filtering Mode
It is set to indicate the DM9102D operate in Inverse filtering mode. This is a read
only bit and decoded from the setup frame of TDES1 bit 28 and bit 22.
Pass Bad Frame
When set, the DM9102 is indicated that receiving the bad frames, including runt
packets and truncated frames, is caused by the FIFO overflow. The bad frame also
has to pass the address filtering if the DM9102D is not set in promiscuous mode.
Hash-only Filter Mode
It is set to indicate the DM9102D operate in Hash-only filtering mode. This is a read
only bit and decoded from the setup frame of TDES1 bit 28 and bit 22.
Receive Start/Stop Command
When set, receive process will begin by fetching the receive descriptor for available
buffer to store the new-coming packet (placed in the running state). If the fetched
descriptor is owned by the host (no descriptor is owned by the DM9102D), the
receive process will enter the suspend state and receive buffer unavailable
CR5<7> sets. Otherwise it runs to wait for the packet’s incoming. When reset,
receive process is placed in the stopped state after completing the reception of the
current frame.
Hash/Perfect Filter Mode
It is set to indicate the DM9102D operate in Hash-only or Hash filtering mode and it
is cleared to indicate the DM9102D operate in Perfect filtering mode. This is a read
only bit and decoded from the setup frame of TDES1 bit 28 and bit 22.
3
PBF
0,RW
2
HOFM
0,RO
1
RXRC
0,RW
0
HPFM
0,RO
6.2.8 Interrupt Mask Register (CR7)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit
16
Name
NISE
Default
0,RW
Description
Normal Interrupt Summary Enable
This bit is set to enable the interrupt for Normal Interrupt Summary.
Normal interrupt includes three conditions:
CR5<0> – TXCI: Transmit Complete Interrupt
CR5<2> – TXDU: Transmit Buffer Unavailable
CR5<6> – RXCI: Receive Complete Interrupt
Abnormal Interrupt Summary Enable
This bit is set to enable the interrupt for Abnormal Interrupt Summary.
Abnormal interrupt includes all interrupt conditions as shown below, excluding
Normal Interrupt conditions. They are TXPS(bit1), TXJT(bit3), TXFU(bit5),
RXDU(bit7), RXPS(bit8), RXWT(bit9), SBE(bit13).
Reserved
System Bus Error Enable
When set together with CR7<15>, CR5<13>, it enables the interrupt for System
Bus Error. The type of system bus error is shown in CR5<24:23>.
Reserved
Receive Watchdog Timer Expired Enable
When this bit and CR7<15>, (CR5<9> are set together, it enable the interrupt of the
condition of the receive watchdog timer expired.
15
AISE
0,RW
14
13
Reserved
SBEE
0,RO
0,RW
12:10
9
Reserved
RXWTE
0,RO
0,RW
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM9102DE | SINGLE CHIP FAST ETHEMET NIC CONTROLLER |
| DM9102 | Single Chip Fast Ethernet NIC controller |
| DM9102A | Single Chip Fast Ethernet NIC controller |
| DM9102AF | Single Chip Fast Ethernet NIC controller |
| DM9102AT | Single Chip Fast Ethernet NIC controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM9102DE | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller |
| DM9102DEP | 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 1 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 128LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 128LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 128LQFP; Data Rate:100Mbps; Ethernet Type:IEEE 802.3u; Supply Voltage Min:2.375V; Supply Voltage Max:2.625V; Digital IC Case Style:LQFP; No. of Pins:128; Interface Type:PCI; Operating Temperature Min:0C;;RoHS Compliant: Yes |
| DM9102H | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller |
| DM9102HEP | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller |
| DM9103 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps 3-port Ethernet Switch Controller with PCI Interface |
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