參數(shù)資料
型號(hào): DM9102D
廠商: Electronic Theatre Controls, Inc.
英文描述: SINGLE CHIP FAST ETHEMET NIC CONTROLLER
中文描述: 單晶片快速以太網(wǎng)NIC控制器
文件頁(yè)數(shù): 52/70頁(yè)
文件大?。?/td> 2245K
代理商: DM9102D
52
Preliminary datasheet
Version: DM9102D-DS-P02
Jan. 14, 2005
The operational sequence from D0 to D3 should be:
Stop TX/RX process
wait for entering stop state
set
test mode, CR6<28:25> = 0011
programming FIFO
contents
exit test mode
enter D3 (hot) state
The sample frame data comparison is completed when the
received frame data has exceeded the programmed frame
length or when the whole packet has been fully received.
The operation procedure is shown below.
CR13: Sample Frame Access Register
Name
TxFIFO
RxFIFO
DiagReset
In DiagReset port there are 7 bits:
Bit 0: Clear TX FIFO write_ address to 0
Bit 1: Clear TX FIFO read_ address to 0
Bit 2: Clear RX FIFO write_ address to 0
Bit 3: Clear RX FIFO read_ address to 0
General definition
Transmit FIFO access port
Receive FIFO access port
General reset for diagnostic pointer port
Bit8:3
32h
35h
38h
Type
R/W
RW
RW
Bit 4: Reserved
Bit 5: Set TX FIFO write_ address to 080H
Bit 6: Set RX FIFO write_ address to 080H
相關(guān)PDF資料
PDF描述
DM9102DE SINGLE CHIP FAST ETHEMET NIC CONTROLLER
DM9102 Single Chip Fast Ethernet NIC controller
DM9102A Single Chip Fast Ethernet NIC controller
DM9102AF Single Chip Fast Ethernet NIC controller
DM9102AT Single Chip Fast Ethernet NIC controller
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