參數(shù)資料
型號： DM9102D
廠商： Electronic Theatre Controls, Inc.
英文描述： SINGLE CHIP FAST ETHEMET NIC CONTROLLER
中文描述： 單晶片快速以太網(wǎng)NIC控制器
文件頁數(shù)： 42/70頁
文件大?。?/td> 2245K
代理商： DM9102D
42
Preliminary datasheet
Version: DM9102D-DS-P02
Jan. 14, 2005
Receive Descriptor Format
RDES0:
31
31
0
OWN
Status
Control bits
Buffer Address
Next Descriptor Address
RDES
0
RDES
1
RDES
2
RDES
3
Buffer Length
Bit 31: OWN, Owner bit of received status
1=owned by DM9102, 0=owned by host
This bit will be reset after packet reception is completed. The
host will set this bit after received data is removed.
15
14
13
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OWN
Frame Length ( FL )
AUN
Bit 30: AUN, Received address unmatched.
Bit 29-16: FL, Frame Length
Frame length indicates total byte count of received packet.
This word-wide content includes status of received frame.
They are loaded after the received buffer that belongs to the
corresponding descriptor is full. All status bits are valid only
when the last descriptor (End Descriptor) bit is set.
Bit 15: ES, Error Summary
It is set for the following error conditions:
Descriptor Unavailable Error (DUE =1), Runt Frame
(RF=1), Excessive Frame Length (EFL=1), Late Collision
Seen (LCS=1), CRC error (CE=1), FIFO Overflow error
(FOE=1). Valid only when ED is set.
Bit 14: DUE, Descriptor Unavailable Error
It is set when the frame is truncated due to the buffer
unavailable. It is valid only when ED is set.
Bit 13,12: LBOM, Loopback Operation Mode or
IP/TCP/UDP checksum status
If CR15 bit 27 is set, these two bits present the IP/TCP/UDP
status:
0X -- IP checksum OK
1X --IP checksum FAIL
X0 – TCP or UDP checksum OK
X1 – TCP or UDP checksum FAIL
; otherwise
these two bits show the received frame is derived from:
12
11
10
9
8
7
6
5
4
3
2
1
0
ES
RF
CE
MF
DUE
LBOM
BD
ED
TLF
LCS
FT
RWT PLE
AE
FOE
00 --- Normal
01 --- Internal loopback
10 --- Internal PHY digital loopback
11 --- Internal PHY analog loopback
Bit 11: RF, Runt Frame
It is set to indicate the received frame has the size smaller
than 64 bytes. It is valid only when ED is set and FOE is
reset.
Bit 10: MF, Multicast Frame
It is set to indicate the received frame has a multicast
address. It is valid only when ED is set.
Bit 9: BD, Begin Descriptor
This bit is set for the descriptor indicating the start of a
received frame.
Bit 8: ED, End Descriptor
This bit is set for descriptor to indicate the end of a received
frame.
Bit 7: EFL, Excessive Frame Length
It is set to indicate the received frame length exceeds 1518
bytes. Valid only when ED is set.
相關(guān)PDF資料
PDF描述
DM9102DE SINGLE CHIP FAST ETHEMET NIC CONTROLLER
DM9102 Single Chip Fast Ethernet NIC controller
DM9102A Single Chip Fast Ethernet NIC controller
DM9102AF Single Chip Fast Ethernet NIC controller
DM9102AT Single Chip Fast Ethernet NIC controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DM9102DE 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller
DM9102DEP 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 1 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 128LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 128LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 128LQFP; Data Rate:100Mbps; Ethernet Type:IEEE 802.3u; Supply Voltage Min:2.375V; Supply Voltage Max:2.625V; Digital IC Case Style:LQFP; No. of Pins:128; Interface Type:PCI; Operating Temperature Min:0C;;RoHS Compliant: Yes
DM9102H 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller
DM9102HEP 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller
DM9103 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps 3-port Ethernet Switch Controller with PCI Interface
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