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參數(shù)資料
| 型號： | DM9161E |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 10/100 Mbps FAST ETHERNET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER |
| 中文描述： | 10/100 Mbps快速以太網(wǎng)物理層單芯片收發(fā)器 |
| 文件頁數(shù)： | 13/47頁 |
| 文件大?。?/td> | 561K |
| 代理商： | DM9161E |
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Final 13
Version: DM9161-DS-F02
May 10,2002
MII Interface (continued)
TXER
synchronously with respect to TXCLK. If TXER is
asserted for one or more clock periods, and TXEN is
asserted, the PHY will emit one or more symbols that
are not part of the valid data delimiter set somewhere in
the frame being transmitted.
(transmit
coding
error)
transitions
are
RXD (receive data) is a nibble (4 bits) of data that are
sampled by the reconciliation sublayer synchronously
with respect to RXCLK. For each RXCLK period which
RXDV is asserted, RXD (3:0) are transferred from the
PHY to the MAC reconciliation sublayer.
RXCLK (receive clock) output to the MAC reconciliation
sublayer is a continuous clock that provides the timing
reference for the transfer of the RXDV, RXD, and
RXER signals.
RXDV (receive data valid) input from the PHY indicates
that the PHY is presenting recovered and decoded
nibbles to the MAC reconciliation sublayer. To interpret
a receive frame correctly by the reconciliation sublayer,
RXDV must encompass the frame, starting no later
than the Start-of-Frame delimiter and excluding any
End-Stream delimiter.
RXER (receive error) transitions are synchronously with
respect to RXCLK. RXER will be asserted for 1 or more
clock periods to indicate to the reconciliation sublayer
that an error was detected somewhere in the frame
being transmitted from the PHY to the reconciliation
sublayer.
CRS (carrier sense) is asserted by the PHY when either
the transmit or receive medium is non-idle, and de-
asserted by the PHY when the transmit and receive
medium are idle. Figure 7-2 depicts the behavior of
CRS during 10Base-T and 100Base-TX transmission.
TXD
Preamble
SFD
Data
EFD
Preamble
SFD
Data
ESD
T/R
J/K
SSD
10Base-T
100Base-TX
TXD
CRS
CRS
IDLE
IDLE
Figure 7-2
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| DM9324 | 5-Bit Comparator |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM9161EP | 制造商:DAVICOM 功能描述:IC TRX 10/100MBPS ENET PHY48LQFP 制造商:DAVICOM 功能描述:IC, TRX, 10/100MBPS, ENET PHY,48LQFP 制造商:DAVICOM 功能描述:CONTROLLER, ETHERNET, 100MBPS, LQFP-48; Data Rate:100Mbps; Ethernet Type:IEEE 802.3u; Supply Voltage Max:3.3V; Digital IC Case Style:LQFP; No. of Pins:48; IC Interface Type:MII, RMII; Package / Case:48-LQFP ;RoHS Compliant: Yes |
| DM9161電路圖-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DM9161電路圖-1 |
| DM9162 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver |
| DM9162EP | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver |
| DM9162NP | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver |
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