DM9331
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
18
Preliminary
Version: DM9331-DS-P02
September 21, 2001
MII Register Description
ADD
00
Name
CONTROL
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
Loop
back
TX FDX
Cap.
FLP Rcv
Ack
LP
Ack
Speed
select
TX HDX
Cap.
Remote
Fault
LP
RF
Auto-N
Enable
Power
Down
Isolate Restart
Auto-N
Full
Duplex
Coll.
Test
Reserved
01
STATUS
T4
Cap.
Next
Page
LP Next
Page
Reserved
Pream.
Supr.
Rsvd
Auto-N
Compl.
Rsvd
Remote
Fault
Auto-N
Cap.
Advertised Protocol Selector Field
Link
Status
Rsvd
Extd
Cap.
04
Auto-Neg.
Advertise
Link Part.
Ability
Auto-Neg.
Expansion
Aux.
Config.
Aux.
Conf/Stat
MDINTR
Reserved
FC
Adv
LP
FC
T4
Adv
LP
T4
TX FDX
Adv
LP
TX FDX
TX HDX
Adv
LP
TX HDX
05
Reserved
LP
10 FDX
LP
10 HDX
Link Partner Protocol Selector Field
06
Reserved
Pardet
Fault
LP Next
Pg Able
Reset
St. Mch
Next Pg
Able
Pream.
Supr.
Auto-N. Monitor Bit [3:0]
New Pg
Rcv
Sleep
mode
LP AutoN
Cap.
Remote
LoopOut
16
BP
4B5B
100
FDX
INTR
PEND
BP
SCR
100
HDX
BP
ALIGN
Reserved
BP_A
DPOK
Rsvd
TX/FX
Select
FEF
Enable
RMCI
Enable
Reserved
Force
100LNK
SPDLE
D_CTL
Rsvd RPDCT
R-EN
17
21
Reserved
FDX
Mask
Rsvd
Link
Mask
INTR
Mask
Reserved
FDX
Change
Rsvd
Link
Change
Rsvd
INTR
Status
Key to Default
In the register description that follows, the default
column takes the form:
<Reset Value>, <Access Type> / <Attribute(s)>
Where
:
<Reset Value>:
1
0
X
(PIN#)
Bit set to logic one
Bit set to logic zero
No default value
Value latched in from pin # at reset
<Access Type>:
RO = Read only
RW = Read/Write
<Attribute (s)>:
SC = Self clearing
P = Value permanently set
LL = Latching low
LH = Latching high