參數(shù)資料
型號： DM93L00
文件頁數(shù)： 120/158頁
文件大?。?/td> 2668K
代理商： DM93L00
Functional Description
The 93L14 consists of four latches with a common active
LOW Enable input and active LOW Master Reset input.
When the Enable goes HIGH, data present in the latches is
stored and the state of the latch is no longer affected by the
S
n
and D
n
inputs. The Master Reset when activated over-
rides all other input conditions forcing all latch outputs LOW.
Each of the four latches can be operated in one of two
modes:
D-TYPE-LATCHDFor D-type operation the S input of a
latch is held LOW. While the common Enable is active the
latch output follows the D input. Information present at the
latch output is stored in the latch when the Enable goes
HIGH.
SET/RESET LATCHDDuring set/reset operation when the
common Enable is LOW a latch is reset by a LOW on the D
input, and can be set by a LOW on the S input if the D input
is HIGH. If both S and D inputs are LOW, the D input will
dominate and the latch wil be reset. When the Enable goes
HIGH, the latch remains in the last state prior to disable-
ment. The two modes of latch operation are shown in the
Truth Table.
Truth Table
MR
E
D
S
Q
n
Operation
H
H
H
L
L
H
L
H
X
L
L
X
L
L
D Mode
Q
n
b
1
H
H
H
H
H
L
L
L
L
H
L
H
L
H
X
L
L
H
H
X
L
H
L
R/S Mode
Q
n
b
1
Q
n
b
1
L
X
X
X
L
RESET
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
Q
n
b
1
e
Previous Output State
Q
n
e
Present Output State
Logic Diagram
TL/F/9612–3
4
相關(guān)PDF資料
PDF描述
DM93L01
DM93L08
DM93L09
DM93L10
DM93L12
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DM93L01 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
DM93L08 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
DM93L09 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
DM93L10 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
DM93L12 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
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