參數(shù)資料
型號(hào)： DMA2271
英文描述： Consumer IC
中文描述： 消費(fèi)性IC
文件頁(yè)數(shù)： 21/36頁(yè)
文件大?。?/td> 496K
代理商： DMA2271
DMA 2271, DMA 2280, DMA 2281
21
3. Functional Description
The DMA 2271, DMA 2280 and DMA 2281 process the
digitized D2–MAC video signal supplied by the VCU
2133 or by the UVC 3130 in the various circuit parts
shown in Fig. 1–4. The resulting digital luminance and
chrominance signals are then reconverted to analog sig-
nals in the VCU or HDAA. The resulting digital audio sig-
nals are processed in the AMU 2481 Audio Mixer which
provides filtering of the medium–quality channels and al-
lows mixing of the four sound channels. The AMU’s digi-
tal output signals are reconverted to analog in the ACP
2371 Audio Processor, which additionally carries out
functions like adjustment of volume, bass and treble,
loudness, etc. Remaining digital data as service and
channel information in packet 0 or line 625 can be han-
dled by software via the IM bus or by additional hardware
which uses the serial B–Data interface (B–Data, B–
Clock and B–Sync). Section 1.2. shows how the DMA
2271, DMA 2280 and DMA 2281 can be used together
with other circuits of I
NTERMETALLS
’s DIGIT 2000 di
-
gital TV system
to realize a multistandard
NTSC/PAL/SECAM/C/
D/D2–MAC color TV receiver.
To understand the signal processing in the DMA 2271,
DMA 2280, and DMA 2281 it may be useful to distin-
guish three different function blocks, namely:
– Clock and Data Recovery
– Video Processing
– Sound/Data Processing
3.1. Clock and Data Recovery
3.1.1. The Code Converter
This circuit converts the digitized C/D/D2–MAC base-
band signal, delivered by the VCU 2133 in a parallel
Gray code, into a simple binary–coded signal. The func-
tion of the circuit is controlled by the CCU 3000 via the
IM bus (see section 4.2.).
3.1.2. The Video Clamping Circuit and the AGC Cir-
cuit
The video clamping circuit measures the DC voltage lev-
el of the clamp period and, by means of the pulse density
modulated signal from pin 48, sets the DC level of the
clamp period to a constant 5.5 V. The white and the black
levels in line 624 are measured for automatic gain con-
trol (AGC pin 49) and the two values are fed to the IM
bus interface which organizes the data communication
with the CCU.
AGC (pin 49) = high if WL – BL < 224
AGC (pin 49) = high impedance if 224
≤
WL – BL
≤
240
AGC (pin 49) = low if WL – BL > 240
3.1.3. The Phase Comparator and the PLL Filter
The phase comparator derives the reference signal from
the slopes contained in the data burst of each line. Its
output signal, an 8–bit word which is passed through a
digital lowpass filter, is added to an 8–bit word, VCOA,
which is provided by the CCU for adjustment of the crys-
tal frequency. This digital PLL signal is output via pins 25
and 26 and routed to the MCU 2600 Clock Generator IC
thus closing the PLL, existing between DMA 2271, DMA
2280, and DMA 2281, VCU 2133 Video Codec and MCU
2600 Clock Generator IC. In this way, the main clock sig-
nal FM of the system is in phase with the duobinary–
coded signal.
To adjust the crystal frequency, it is possible to render in-
operative the PLL by setting PLLO bit 4 in address 201
(Table 4–1). The VCO in the MCU is then free–running
and the center frequency can be aligned by varying the
data word VCOA (bits 0 to 7) in the IM bus address 14.
3.1.4. The Data Slicer and the Synchronization Cir-
cuit
The digitized C/D/D2–MAC baseband signal is filtered
by a 5 MHz lowpass filter before being routed to the data
slicer. The output of the slicer is connected to pin 59 (B–
Data). In phase with the continuous bit stream of 20.25
or 10.125 MBit/s, a clock signal (B–Clock), a synchroni-
zation signal (B–Sync) and a signal for Teletext informa-
tion (TTSYNC) are available at pins 60, 58, and 57 (see
Fig. 2–15).
The vertical synchronization pulse, on–chip, is derived
from a 64–bit correlator which compares the data stream
at the output of the slicer with the fixed Frame Synchroni-
zation Word (FSW). Whenever the correlation is equal
to or greater than 61 a frame reset pulse is generated.
Horizontal synchronization is derived by counting. In
phase with the video outputs (L0 to L7, C0 to C7), the
various synchronization and blanking signals are out-
puts at pins 50 to 53 (Fig. 2–17, 2–18 and 2–18).
3.2. Video Processing
The DMA 2271, DMA 2280, and DMA 2281 process the
C/D/D2–MAC baseband signal, digitized by the VCU or
UVC at a sample frequency of 20.25 MHz. For time ex-
pansion, the video samples of each line are stored in an
on–chip RAM and read to at the lower frequencies of
13.5 MHz for the luminance signal and 6.75 MHz for the
color difference signals.
3.2.1. The Luminance Store
Time expansion of the luminance signal is achieved by
digitizing the analog signal at a clock frequency of 20.25
MHz, storing the Bytes, and reading them at a frequency
of 13.5 MHz. For this, a fast RAM is provided on–chip.
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