參數(shù)資料
型號(hào): DMA2271
英文描述: Consumer IC
中文描述: 消費(fèi)性IC
文件頁數(shù): 31/36頁
文件大?。?/td> 496K
代理商: DMA2271
Bits must be set to zero for write registers (W) and
are don’t care for read registers (R)
Bits not used in DMA 2280 registers, but in other devices
DMA 2271, DMA 2280, DMA 2281
31
Table 4–3:
DMA control and status registers, graphical overview
Addr.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
14
23
200
201
202
203
194
195
196
197
198
199
204
205
VCOS
VCOA
VCO Adjustment
0
0
SAV
Saturation V
40
0
CT
Luma Contrast
32
LD
CFI
Chroma Filter
0
MSB
LSB
Luma Delay
DGC
Disable
Gray
0
0
0
CSP
0
0
CSP
SD
Composite Sync. Delay
64
0
0
BD
Blank Delay
64
L
S
HQ
H
C1M
Channel Mode
C1U
Mode
0
C1A
Channel Packet Addres
100
C2A
Channel Packet Address
100
C3A
Channel Packet Address
100
C4A
Channel Packet Address
100
SFS
Subframe Select
7
FCD
Data
0
ClLoop
Gain
2
Direct.
W
W
W
W
W
W
W
W
W
W
W
W
W
W
DI3
DI2
DI1
0
0
0
0
0
1
0
SAU
Saturation U
28
0
0
0
CSE
0
CTS
0
6
0
0
0
CMP
Chroma
Mult.
0
STA
Stand
alone
0
PLLO
PLL
open
0
NIN
Non
Interl.
0
DLC
Disable
L/C
0
DCL
Clamp.
off
0
DSY
Disable
Sync.
0
L525
525
lines
LFI
Luma Filter
C1E
Enable
1
L
S
HQ
H
C2M
Channel Mode
C2U
Mode
0
C2E
Enable
1
L
S
HQ
H
C3M
Channel Mode
C3U
Mode
Update
0
C3E
Channel
Enable
0
L
HQ
H
C4M
Channel Mode
C4U
Mode
Update
0
C4E
Channel
Enable
0
DRS
Rate
1
CD
Chip
0
AUM
Auto
0
0
0
CS
Chip
Select
0
0
0
0
0
0
0
BPH
Burst
0
SLL
Slice Level
0
0
0
EDC
Energy Dispersal
Compensation
2
PLLG
PLL
2
SLS
Slicer
1
ENF2
Filters
0
PLLT
PLL
0
ACF
Audio
0
ACS
Switch
0
DSB
S_Bus
0
P0C
P0
0
P0R
RP0
0
DGT
Data Group Type
0
SBE
S_Bus Enable
3
0
0
0
206
BER
Bit Error Rate
R
207
WL
White Level
R
208
C4L
Coding Law CH4
R
209
PSL
Packet 0 Syndrom Low Byte
R
210
PDL
Packet 0 Data Low Byte
R
T15
0
T14
1
T13
0
T12
0
T11
0
T10
0
T9
0
T8
0
T7
0
T6
0
T5
0
T4
0
T3
0
T2
0
T1
0
T0
0
VER
Version
SYNC
P0S
C49
C39
C29
C19
Status
BL
Black Level
L
S
HQ
H
L
S
HQ
H
L
S
HQ
H
L
S
HQ
H
C3L
Coding Law CH3
C2L
Coding Law CH2
C1L
Coding Law CH1
PSH
Packet 0 Syndrom High Byte
PDH
Packet 0 Data High Byte
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