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| 型號： | DMA2271 |
| 英文描述： | Consumer IC |
| 中文描述： | 消費(fèi)性IC |
| 文件頁數(shù)： | 25/36頁 |
| 文件大?。?/td> | 496K |
| 代理商： | DMA2271 |
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DMA 2271, DMA 2280, DMA 2281
25
4. The Three Serial Interfaces
4.1. The S Bus Interface and the S Bus
The S bus has been designed to connect the digital
sound output of the DMA 2271, DMA 2280, and DMA
2281 MAC Decoders or the MSP 2400 NICAM Demodu-
lator/Decoder to audio–processing ICs such as the AMU
2481 Audio Mixer or the ACP 2371 Audio Processor
etc., and to connect these ICs one to the other. The S bus
is a unidirectional, digital bus which transmits the sound
information in one direction only, so that it is not neces-
sary to solve priority problems on the bus.
The S bus consists of the three lines: S–Clock, S–Ident,
and S–Data. The DMA 2271, DMA 2280, and DMA 2281
or the MSP 2400 generates the signals S–Clock and S–
Ident, which control the data transfer to and between the
various processors which follow the DMA 2271, DMA
2280, and DMA 2281 or the MSP 2400. For this, the S–
Clock and S–Ident inputs of all processors in the system
are connected to the S–Clock and S–Ident outputs of the
DMA 2271, DMA 2280, and DMA 2281 or the MSP 2400.
S–Data output of the DMA 2271, DMA 2280, and DMA
2281 or MSP 2400 is connected to the S–Data input of
the next following AMU, the AMU’s S–Data output is
connected to the ACP’s S–Data input and so on.
The sound information is transmitted in frames of 64 bits,
divided into four successive 16–bit samples. Each sam-
ple represents one sound channel. The timing of a com-
plete transmission of four samples is shown in Fig. 2–14,
the times are specified under “Recommended Operat-
ing Conditions”. The transmission starts with the LSB of
the first sample. The S–Clock signal is used to write the
data into the receiver’s input register. the S–Ident signal
marks the end of one frame of 64 bits and is used as latch
pulse for the input register. The repetition rate of S–Ident
pulses is identical to the sampling rate of the D2–MAC
or NICAM sound signal; thus it is possible to transfer four
sound channels simultaneously.
The S bus interface of the DMA 2271, DMA 2280, and
DMA 2281 mainly consists of an output register, 64–bit
wide. The timing to write bit by bit is supplied by the S–
Clock signal. In the case of an S–Ident pulse, the con-
tents of the output register are written to the S–Data out-
put.
4.2. The IM Bus Interface and the IM Bus
4.2.1. The IM Bus
The INTERMETALL Bus (IM Bus for short) was de-
signed to control the DIGIT 2000 ICs by the CCU Central
Control Unit. Via this bus the CCU can write data to the
ICs or read data from them. This means the CCU acts
as a master, whereas all controlled ICs have purely
slave status.
The IM bus consists of three lines for the signals Ident
(ID), Clock (CL) and Data (D). The clock frequency
range is 50 Hz to 1 MHz. Ident and clock are unidirec-
tional from the CCU to the slave ICs, Data is bidirection-
al. bidirectionality is achieved by using open–drain out-
puts. The 2.5 ... 1 kOhm pull–up resistor common to all
outputs must be connected externally.
The timing of a complete IM Bus transaction is shown in
Fig. 5–2. In the non–operative state the signals of all
three bus lines are High. To start a transaction the CCU
sets the ID signal to Low level, indicating an address
transmission, and sets the CL signal to Low level, as well
as to switch the first bit on the Data line. Then eight ad-
dress bits are transmitted, beginning with the LSB. Data
takeover in the slave ICs occurs at the positive edge of
the clock signal. At the end of the address byte the ID sig-
nal switches to High, initiating the address comparison
in the slave circuits. In the addressed slave, the IM bus
interface switches over to Data read or write, because
these functions are correlated to the address. Also con-
trolled by the address the CCU now transmits eight or
sixteen clock pulses, and accordingly one or two bytes
of data are written into the addressed IC or read out from
it, beginning with the LSB.
The completion of the bus transaction is signalled by a
short Low state pulse of the ID signal. This initiates the
storing of the transferred data.
For future software compatibility, the CCU must write a
zero into all bits not used at present. Reading undefined
or unused bits, the CCU must adopt “don’t” care behav-
ior.
4.2.2. IM Bus Addresses and Instructions
By means of the IM bus, the DMA 2271, DMA 2280, and
DMA 2281 communicate with the CCU 3000 Central
Control Unit. The DMA 2271, DMA 2280, and DMA 2281
receive the instructions for the user–actuated settings
such as color saturation, contrast, sound channel select,
packet 0 control, etc., and transmits the measured or re-
ceived values such as bit error rate, signal level, sound
coding mode,packet 0 data, etc. The address numbers
and the associated data for this interaction via the IM bus
are shown in Tables 4–1 to 4–4. In these tables “W”
means data written by the CCU into the DMA, and “R”
means data read by the CCU from the DMA.
4.3. The Burst Bus
The Burst bus serves for transfer of the digitized
D2–MAC baseband signal, after code conversion, low-
pass filtering and slicing as described in sections 3.1.1.
and 3.1.4., to e.g., the TPU 2735 Teletext Processor or
the DMA 2275/DMA 2285/DMA 2286 MAC Descram-
bler. Timing of the B bus is shown in Fig. 2–15 and under
Recommended Operating Conditions.
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| DMA2281 | Consumer IC |
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相關(guān)代理商/技術(shù)參數(shù) |
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| DMA22734 | 制造商:Endicott Research Group Inc (ERG) 功能描述:5V DC TO AC INVERTER - Bulk |
| DMA22734F | 制造商:Endicott Research Group Inc (ERG) 功能描述:CCFL Inverter Dual Lamp 40KHz 12-Pin 制造商:Endicott Research Group Inc (ERG) 功能描述:INVERTER ROHS - Bulk 制造商:ERG 功能描述:DMA Series Dual Lamp 5 V Input Dimming Inverter |
| DMA2275 | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:DMA 2275, DMA 2286 C/D/D2-MAC Descrambler |
| DMA2280 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Consumer IC |
| DMA2281 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Consumer IC |
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