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參數(shù)資料
| 型號(hào)： | DMC73C168 |
| 英文描述： | 8Bit Single Chip Microcontroller |
| 中文描述： | 8位單芯片微控制器 |
| 文件頁數(shù)： | 28/90頁 |
| 文件大?。?/td> | 742K |
| 代理商： | DMC73C168 |
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28
8Bit Single Chip Microcontroller
DMC73C167
Table 5-9. P12 010Ch DDATA D Port Data
Bit
R
W
7
6
5
4
3
2
1
0
-
-
-
-
DDATA3
DDATA2
DDATA1
DDATA0
Table 5-10. D Port Control Register Operation
DDDRn
0
Driection
Input Port
DDATAn(Read)
0 ; Input 'Low'
1 : Input 'High'
Written Data
DDATAn(Write)
Invalid
1
Output Port
0 ; Output 'Low'
1 : Output 'High'
5.2 Device Initialization
Interrupt level 0 (RESET) cannot be masked and will be recognized immediately, even in the
middle of an instruction. To execute the level-0 interrupt, the RESET pin must be held low
for a minimum of five internal clock cycles to guarantee recognition by the device. During
assertion of the RESET pin, the following operations are performed prior to the first
instruction acquisition.
1) All zeros are written to the status register. This disables all interrupts and clears all interrupt
flags.
2) The initialized data is written to the peripheral register.
3) The MSB and LSB values of the program counter just before RESET are stored in the R0
and R1 (A and B) registers, respectively.
4) The stack pointer is initialized to 01h.
5) The MSB and LSB of the reset vector are fetched from locations FFFEh and FFFFh,
respectively (see Table 4-5), and located into the program counter.
5.3 I/O Control Registers
The I/O control registers are lcated in the peripheral file and are responsible for interrupt
control. The DMC73C167 contains the I/O Control 0 (IOCTL0), I/O Control 1 (IOCTL1),
I/O Control 2 (IOCTL2), I/O Control 3 (IOCTL3), and I/O Control 4 (IOCTL4) registers, the
I/O Control registers are mapped into lcations P0 (IOCTL0), P1 (IOCTL1), P2 (IOCTL2), P3
￡￡á￡￡×￡￡
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