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參數(shù)資料
| 型號(hào)： | DMC73C168 |
| 英文描述： | 8Bit Single Chip Microcontroller |
| 中文描述： | 8位單芯片微控制器 |
| 文件頁(yè)數(shù)： | 34/90頁(yè) |
| 文件大小： | 742K |
| 代理商： | DMC73C168 |
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34
8Bit Single Chip Microcontroller
DMC73C167
Bit 3
INT5_1F. I2C MASTER Interrupt 5_1 Flag.
This flag sets the INT5F bit of IOCTL1 register and requests to jump to the
INT5 interrupt service routine. INT5_1F is cleared when 1 is written to the
INT5_1C bit of the I2C MSTS register (P50.7).
0 = I2C MASTER interrupt (INT5_1) is not requested.
1 = I2C MASTER interrupt (INT5_1) is pending.
Note : See I2C master status register MSTS for details.
INT5_2E. I2C SLAVE Interrupt 5_2 Enable
0 = Disables I2C SLAVE Interrupt (INT5_2).
1 = Enable I2C MASTER Interrupt (INT5_2)
INT5_2F. I2C SLAVE Interrupt 5_2 Flag
This flag sets the INT5F bit of IOCTL1 register and requests to jump to the
INT5 interrupt service routine. INT5_2F is cleared when 1 is written to the
INT5_2C bit of the SCTL register (P56.0).
0 = I2C SLAVE Interrupt (INT5_2) is not requested.
1 = I2C SLAVE Interrupt (INT5_2) is pending
Not used in this device.
Bit 4
Bit 5
Bit 6, 7
5.4 Interrupt Logic and External Interrupt
The internal interrupt logic for each of the five maskable interrupts for the DMC73C167
is shown in Figures 5-1 and 5-2 below. This interrupt logic will detect the output of each
corresponding interrupt.
Figure 5-1. Interrupt Logic (n = 2 or 4 ; m = 0 or 1)
￡￡á￡￡×￡￡
R
S
Q
INTn_mC
INTn_m
Input
INTn_mE
INTnF
Read
Interrupt Enable
(ST : Status Register)
INTn
Happen
Write
Read
Enable Latch
INTn Enable
INTnE
Q
D
InmFLG
Read
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