參數(shù)資料
型號: DOC0508
英文描述: 8-bit Microcontroller with Flash(57.64 k)
中文描述: 8位閃存(57.64畝微控制器)
文件頁數(shù): 4/7頁
文件大小: 57K
代理商: DOC0508
next FPGA in the chain is ready to accept the new configu-
ration information, and so on.
Another possibility is to connect all /CS lines to the micro-
controller so that it can select the next FPGA to be config-
ured. All other lines are brought to all FPGAs in parallel. In
this case normal bitstreams are sufficient, not the special
bitstream that is explicitly generated and contains several
preambles as described above.
If an error occurs during configuration, the microcontroller
can detect this through the /ERR line. When the error is
detected from the FPGA, e.g., an invalid preamble, this
line will be pulled low to indicate the error to the microcon-
troller. When using several FPGAs the error lines can all
be connected since this is an open collector output that
can be WIRE-OR’ed. The microcontroller asserts the
/CHECK line to determine whether the FPGA is reconfig-
ured. It also compares the bitstream it receives with the
information that is already stored in the configuration
memory within the FPGA. In the case of a difference the
/ERR line is asserted.
If only reconfiguration of the FPGA without wanting error
detection, the number of lines are reduced to three. /CS is
tied to GND so that the FPGA is always selected. The mi-
crocontroller only has to provide the signals /CON, the
configuration clock CCLK, and the data line. This solution
uses the least board space.
With parallel data transfer, as shown in Figure 5, 8 data
lines instead of one are used to transfer one data byte in-
stead of one data bit per clock cycle. The configuration
time is therefore much shorter. For these data lines, the
normal data bus of the microcontroller is used, and the
data transfer is controlled through the /WR signal of the
controller. Reconfiguration of the FPGA is just like writing
to an external RAM.
For a system where reconfiguration of the FPGA makes
part of the regular system function this might be the most
flexible solution. In this mode 6 as illustrated in the data
book several FPGAs are cascaded as well. In this case, all
lines except for /CS are brought to all FPGAs in parallel.
/CS is connected to /CSOUT of the preceding FPGA in the
chain to configure several FPGAs with one bitstream. The
microcontroller can control the /CS pins to select the
FPGA to be reconfigured as in a memory-mapped ap-
proach. The exact timing is shown in Figure 6.
Options for Storing Configuration Data
For storing the configuration data within the system there
are different possibilities, each having its advantages and
disadvantages.
The first possibility consists of using the internal memory
of a controller to store the configuration information. At first
glance this might look like a waste but it offers distinctive
advantages that enable certain applications. The micro-
controller AT89C51 has an internal memory of 4 Kbytes,
so that a full configuration of the AT6002 and an additional
1.4 Kbytes of program are stored. In this case only two
chips make up the whole system which saves board
space. The configuration data is also protected by the lock
bits of the controller preventing it from being reverse-engi-
neered.
Another possibility is to store the data in a parallel flash or
EPROM memory that is handled by the microcontroller. If
a flash memory is used, the configurations are changed
through the serial link of the microcontroller simply by
downloading a new configuration into the flash memory.
Depending on the size of the memory, many configura-
tions are stored in the system. For example, for a 5000
gate FPGA, the AT6005, requires only 8 Kbytes of con-
figuration data. The address space of an AT89C51 con-
troller is 64 Kbytes of data memory. This amounts to eight
M0,1,2
/CON
/CS
/CCLK
D0..7
Preamble
6
Figure 6.
FPGA Select Timing
4-24
Microcontroller
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