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參數(shù)資料
| 型號： | DOC0508 |
| 英文描述： | 8-bit Microcontroller with Flash(57.64 k) |
| 中文描述： | 8位閃存（57.64畝微控制器） |
| 文件頁數(shù)： | 7/7頁 |
| 文件大?。?/td> | 57K |
| 代理商： | DOC0508 |
Encryption and Security
SRAM-based FPGAs always receive their configuration
from the outside. Besides all advantages this offers, e.g.,
reconfigurability or testability, there can be problems with
security and protection of the design. When the configura-
tion is stored in a serial or parallel memory that is read
directly by the FPGA, this memory can be copied. In this
case no protection is available.
The problem is only half as difficult as it seems because
simply copying the configuration is not the whole job. This
can only be used to copy the system, but the logic function
of the FPGA is very difficult to deduce from the bitstream.
The relation between a certain bit in the bitstream and the
function it controls is very difficult to determine. Therefore,
the circuit realized with the FPGA is very difficult to re-
verse-engineer.
When using a microcontroller to configure the FPGA, ad-
ditional security mechanisms are implemented. The bit-
stream can be encrypted before storing it in the system
memory so that the microcontroller decrypts the bitstream
before sending it to the FPGA. The key is hidden within the
microcontroller or with external means, e.g., a smartcard
or identification number.
Even with very basic operations a high degree of security
is reached. For example, if all bits of the bitstream are in-
verted the configuration bitstream is useless for the FPGA.
Another way is to exchange some bytes with others
through a table. This is a very easy and therefore fast op-
eration that will slightly slow down the configuration proc-
ess and will result in a high level of protection.
Using the option indicated above (storing the configuration
information within the internal memory of the controller)
has other advantages. With the lock bits of the controller
access to the memory can be inhibited even when the mi-
crocontroller is put on a programmer. With the chip-erase
function of the Atmel microcontrollers, the whole memory
array can be erased in 10ms when the part of the system
is accessed, e.g., by opening the case or entering a wrong
identification number three times. This also works when
the configuration is not stored within the microcontroller,
but only the key number is stored.
There are still weak points in the system. These are made
up by the data and control lines between the FPGA and
the microcontroller. They are sampled with a logic ana-
lyzer and the configuration information is extracted from
the timing diagram. This is difficult, but not impossible.
One needs to know the parts that are used in the system;
the right key or identification number, and a running sys-
tem for analyzing it. Only then the configuration for one
given moment is known. It does not infer that the system
can be copied. If partial reconfiguration is used, the design
can be partitioned in two or more parts. The major part is
transferred unencrypted and some few cells of central im-
portance are transferred at another point of time or from
the outside. A system that changes itself frequently is
much harder to copy or reverse-engineer. Other tricks
such as custom-marking the FPGA (so it is thought to be
an ASIC), additional power and ground pins help to dis-
guise the identity of the used part. By implementing all
these methods, the process of copying the design is com-
plicated, but there is no absolute security.
Conclusion
The following table shows the different options for parallel
or serial configurations in conjunction with parallel or serial
configuration storage. The given configuration times are
for full configuration of an AT6005 without encryption. An
AT89C51 microcontroller with a clock frequency of 24
MHz is used. For assessing the necessary board space, it
was assumed that the microcontrollers are used with QFP
packages and the memories are used in SOIC or TSOP
packages.
Connection to
FPGA
External
Memory
Space
Requirements
Configuration
Time
Serial
Serial
Parallel
Parallel
Serial
Parallel
Serial
Parallel
199mm
2
329mm
2
199mm
2
329mm
2
93ms
61ms
61ms
30ms
The space requirements are mainly determined by the
chosen memory. It is difficult to assess the board space
required by parallel or serial wiring. Either one will be de-
termined by application requirements, that is, fast recon-
figuration or small space. Configuration time is more de-
pendent on the connection between the controller and the
FPGA; the memory connection is not as important.
It is obvious that controlling the configuration of FPGAs
with the help of microcontrollers is implemented very eas-
ily. When a controller is already in use within the system,
only one additional port is required, and some space in the
flash memory that might already be in the system as well.
Flexibility in the design is increased and additional fea-
tures can easily be implemented.
Microcontroller
4-27
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