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參數(shù)資料
| 型號： | DP83848HSQ/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 11/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX ETHERNET PHYTER 40-LLP |
| 產(chǎn)品培訓模塊： | PHYTER® Family |
| 標準包裝： | 1 |
| 類型： | 收發(fā)器 |
| 驅動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | 以太網(wǎng) |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 40-LLP-EP（6x6） |
| 包裝： | 剪切帶 (CT) |
| 配用： | DP83848H-MAU-EK-ND - BOARD EVALUATION DP83848H |
| 其它名稱： | *DP83848HSQ/NOPB DP83848HSQCT |
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2.4 LED Interface
The DP83848H supports a configurable Light Emitting
Diode (LED) pin for configuring the link. The PHY Control
Register (PHYCR) for the LED can also be selected
through address 19h, bit [5].
See Table 3 for LED Mode selection.
The LED_LINK pin in Mode 1 indicates the link status of
the port. In 100BASE-T mode, link is established as a
result of input receive amplitude compliant with the TP-
PMD specifications which will result in internal generation
of signal detect. A 10 Mb/s Link is established as a result of
the reception of at least seven consecutive normal Link
Pulses or the reception of a valid 10BASE-T packet. This
will cause the assertion of LED_LINK. LED_LINK will deas-
sert in accordance with the Link Loss Timer as specified in
the IEEE 802.3 specification.
The LED_LINK pin in Mode 1 will be OFF when no LINK is
present.
The LED_LINK pin in Mode 2 will be ON to indicate Link is
good and BLINK to indicate activity is present on either
transmit or receive activity.
Since the LED_LINK pin is also used as a strap option, the
polarity of the LED is dependent on whether the pin is
pulled up or down.
2.4.1 LED
Since the Auto-Negotiation (AN0) strap option shares the
LED_LINK output pin, the external components required
for strapping and LED usage must be considered in order
to avoid contention.
Specifically, when the LED output is used to drive the LED
directly, the active state of the output driver is dependent
on the logic level sampled by the AN0 input upon power-
up/reset. For example, if the AN0 input is resistively pulled
low then the corresponding output will be configured as an
active high driver. Conversely, if the AN0 input is resistively
pulled high, then the corresponding output will be config-
ured as an active low driver.
Refer to Figure 3 for an example of AN0 connection to
external components. In this example, the AN0 strapping
results in Auto-Negotiation with 10/100 Half/Full-Duplex
advertised.
The adaptive nature of the LED output helps to simplify
potential implementation issues of this dual purpose pin..
2.4.2 LED Direct Control
The DP83848H provides another option to directly control
thel LED output through the LED Direct Control Register
(LEDCR), address 18h. The register does not provide read
access to the LED.
Table 3. LED Mode Select
Mode
LED_CFG[0]
(bit 5)
or (pin33)
LED_LINK
1
ON for Good Link
OFF for No Link
2
0
ON for Good Link
BLINK for Activity
LE
D
_LIN
K
VCC
11
0
AN0
=
1
2.
2k
Figure 3. AN0 Strapping and LED Loading Example
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DP83848I | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Industrial Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver |
| DP83848I_08 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PHYTER? - Industrial Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver |
| DP83848I-MAU-EK | 功能描述:BOARD EVALUATION DP83848I RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| DP83848I-MAU-EK/NOPB | 功能描述:以太網(wǎng)開發(fā)工具 DP83848 MAU CARD IND TEMP RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
| DP83848I-POE-EK | 功能描述:以太網(wǎng)開發(fā)工具 DP83848 POE CARD IND TEMP RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
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