- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1912 > DP83848HSQ/NOPB (National Semiconductor)IC TXRX ETHERNET PHYTER 40-LLP PDF資料下載
參數(shù)資料
| 型號(hào)： | DP83848HSQ/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 24/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX ETHERNET PHYTER 40-LLP |
| 產(chǎn)品培訓(xùn)模塊： | PHYTER® Family |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | 以太網(wǎng) |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 40-LLP-EP（6x6） |
| 包裝： | 剪切帶 (CT) |
| 配用： | DP83848H-MAU-EK-ND - BOARD EVALUATION DP83848H |
| 其它名稱： | *DP83848HSQ/NOPB DP83848HSQCT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當(dāng)前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁
29
www.national.com
DP
83
84
8
H
4.2.7 Descrambler
A serial descrambler is used to de-scramble the received
NRZ data. The descrambler has to generate an identical
data scrambling sequence (N) in order to recover the orig-
inal unscrambled data (UD) from the scrambled data (SD)
as represented in the equations:
Synchronization of the descrambler to the original scram-
bling sequence (N) is achieved based on the knowledge
that the incoming scrambled data stream consists of
scrambled IDLE data. After the descrambler has recog-
nized 12 consecutive IDLE code-groups, where an
unscrambled IDLE code-group in 5B NRZ is equal to five
consecutive ones (11111), it will synchronize to the receive
data stream and generate unscrambled data in the form of
unaligned 5B code-groups.
In order to maintain synchronization, the descrambler
must continuously monitor the validity of the unscrambled
data that it generates. To ensure this, a line state monitor
and a hold timer are used to constantly monitor the syn-
chronization status. Upon synchronization of the descram-
bler the hold timer starts a 722
s countdown. Upon
detection of sufficient IDLE code-groups (58 bit times)
within the 722
s period, the hold timer will reset and
begin a new countdown. This monitoring operation will
continue indefinitely given a properly operating network
connection with good signal integrity. If the line state mon-
itor does not recognize sufficient unscrambled IDLE code-
groups within the 722
s period, the entire descrambler
will be forced out of the current state of synchronization
and reset in order to re-acquire synchronization.
4.2.8 Code-group Alignment
The code-group alignment module operates on unaligned
5-bit data from the descrambler (or, if the descrambler is
bypassed, directly from the NRZI/NRZ decoder) and con-
verts it into 5B code-group data (5 bits). Code-group align-
ment occurs after the J/K code-group pair is detected.
Once the J/K code-group pair (11000 10001) is detected,
subsequent data is aligned on a fixed boundary.
4.2.9 4B/5B Decoder
The code-group decoder functions as a look up table that
translates incoming 5B code-groups into 4B nibbles. The
code-group decoder first detects the J/K code-group pair
preceded by IDLE code-groups and replaces the J/K with
MAC preamble. Specifically, the J/K 10-bit code-group
pair is replaced by the nibble pair (0101 0101). All subse-
quent 5B code-groups are converted to the corresponding
4B nibbles for the duration of the entire packet. This con-
version ceases upon the detection of the T/R code-group
pair denoting the End of Stream Delimiter (ESD) or with
the reception of a minimum of two IDLE code-groups.
4.2.10 100BASE-TX Link Integrity Monitor
The 100 Base TX Link monitor ensures that a valid and
stable link is established before enabling both the Trans-
mit and Receive PCS layer.
Signal detect must be valid for 395us to allow the link
monitor to enter the 'Link Up' state, and enable the trans-
mit and receive functions.
4.2.11 Bad SSD Detection
A Bad Start of Stream Delimiter (Bad SSD) is any transi-
tion from consecutive idle code-groups to non-idle code-
groups which is not prefixed by the code-group pair /J/K.
If this condition is detected, the DP83848H will assert
RX_ER and present RXD[3:0] = 1110 to the MII for the
cycles that correspond to received 5B code-groups until at
least two IDLE code groups are detected. In addition, the
False Carrier Sense Counter register (FCSCR) will be
incremented by one.
Once at least two IDLE code groups are detected, RX_ER
and CRS become de-asserted.
4.3 10BASE-T TRANSCEIVER MODULE
The 10BASE-T Transceiver Module is IEEE 802.3 compli-
ant. It includes the receiver, transmitter, collision, heart-
beat, loopback, jabber, and link integrity functions, as
defined in the standard. An external filter is not required
on the 10BASE-T interface since this is integrated inside
the DP83848H. This section focuses on the general
10BASE-T system level operation.
4.3.1 Operational Modes
The DP83848H has two basic 10BASE-T operational
modes:
— Half Duplex mode
— Full Duplex mode
Half Duplex Mode
In Half Duplex mode the DP83848H functions as a stan-
dard IEEE 802.3 10BASE-T transceiver supporting the
CSMA/CD protocol.
Full Duplex Mode
In Full Duplex mode the DP83848H is capable of simulta-
neously transmitting and receiving without asserting the
collision signal. The DP83848H's 10 Mb/s ENDEC is
designed to encode and decode simultaneously.
UD
SD
N
⊕
()
=
SD
UD
N
⊕
()
=
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DP83848YB/NOPB | IC TXRX ETHERNET PHYTERA 48-LQFP |
| DRM4000-N00-232 | DRM 4000 MODULE |
| DRM4000L-N00-232 | MODULE DEAD RECKONING RS-232 |
| DS100BR111SQE/NOPB | IC REPEATER 10.3GBPS 2CH 24LLP |
| DS10BR254TSQX/NOPB | IC LVDS REPEAT 1.5GBPS 1:4 40LLP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DP83848I | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Industrial Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver |
| DP83848I_08 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PHYTER? - Industrial Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver |
| DP83848I-MAU-EK | 功能描述:BOARD EVALUATION DP83848I RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| DP83848I-MAU-EK/NOPB | 功能描述:以太網(wǎng)開發(fā)工具 DP83848 MAU CARD IND TEMP RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
| DP83848I-POE-EK | 功能描述:以太網(wǎng)開發(fā)工具 DP83848 POE CARD IND TEMP RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。