參數(shù)資料
型號： DP83848YB-EVK/NOPB
廠商： National Semiconductor
文件頁數(shù)： 29/86頁
文件大?。?/td> 0K
描述： EVAL BOARD PHYTER EXTREME TEMP
標準包裝： 1
主要目的： 接口，以太網(wǎng)
已用 IC / 零件： DP83848YB
已供物品： 板
www.national.com
34
D
P
838
48
YB
5.2 ESD Protection
Typically, ESD precautions are predominantly in effect
when handling the devices or board before being installed
in a system. In those cases, strict handling procedures
need be implemented during the manufacturing process to
greatly reduce the occurrences of catastrophic ESD
events. After the system is assembled, internal compo-
nents are less sensitive from ESD events.
See Section 8.0 for ESD rating.
5.3 Clock In (X1) Requirements
The DP83848YB supports an external CMOS level oscilla-
tor source or a crystal resonator device.
Oscillator
If an external clock source is used, X1 should be tied to the
clock source and X2 should be left floating.
Specifications for CMOS oscillators: 25 MHz in MII Mode
and 50 MHz in RMII Mode are listed in Table 7 and Table 8.
Crystal
A 25 MHz, parallel, 20 pF load crystal resonator should be
used if a crystal source is desired. Figure 12 shows a typi-
cal connection for a crystal resonator circuit. The load
capacitor values will vary with the crystal vendors; check
with the vendor for the recommended loads.
The oscillator circuit is designed to drive a parallel reso-
nance AT cut crystal with a minimum drive level of 100
W
and a maximum of 500
W. If a crystal is specified for a
lower drive level, a current limiting resistor should be
placed in series between X2 and the crystal.
As a starting point for evaluating an oscillator circuit, if the
requirements for the crystal are not known, CL1 and CL2
should be set at 33 pF, and R1 should be set at 0.
Specification for 25 MHz crystal are listed in Table 9.
Figure 12. Crystal Oscillator Circuit
X1
X2
CL2
CL1
R1
Table 7. 25 MHz Oscillator Specification
Parameter
Min
Typ
Max
Units
Condition
Frequency
25
MHz
Frequency
Tolerance
+50
ppm
Operational
Temperature
Frequency
Stability
+50
ppm
1 year aging
Rise / Fall Time
6
nsec
20% - 80%
Jitter
8001
psec
Short term
Jitter
8001
psec
Long term
Symmetry
40%
60%
Duty Cycle
1 This limit is provided as a guideline for component selection and to guaranteed by production testing.
Refer to AN-1548, “PHYTER 100 Base-TX Reference Clock Jitter Tolerance,“ for details on jitter performance.
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