參數(shù)資料
型號(hào): DP83848YB/NOPB
廠商: National Semiconductor
文件頁(yè)數(shù): 18/86頁(yè)
文件大?。?/td> 0K
描述: IC TXRX ETHERNET PHYTERA 48-LQFP
標(biāo)準(zhǔn)包裝: 250
類型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: 以太網(wǎng)
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-LQFP 裸露焊盤(7x7)
包裝: 帶卷 (TR)
其它名稱: DP83848YBTR
www.national.com
24
D
P
838
48
YB
4.0 Architecture
This section describes the operations within each trans-
ceiver module, 100BASE-TX and 10BASE-T. Each opera-
tion consists of several functional blocks and described in
the following:
— 100BASE-TX Transmitter
— 100BASE-TX Receiver
— 10BASE-T Transceiver Module
4.1 100BASE-TX TRANSMITTER
The 100BASE-TX transmitter consists of several functional
blocks which convert synchronous 4-bit nibble data, as pro-
vided by the MII, to a scrambled MLT-3 125 Mb/s serial
data stream. Because the 100BASE-TX TP-PMD is inte-
grated, the differential output pins, PMD Output Pair, can
be directly routed to the magnetics.
The block diagram in Figure 6. provides an overview of
each functional block within the 100BASE-TX transmit sec-
tion.
The Transmitter section consists of the following functional
blocks:
— Code-group Encoder and Injection block
— Scrambler block (bypass option)
— NRZ to NRZI encoder block
— Binary to MLT-3 converter / Common Driver
The bypass option for the functional blocks within the
100BASE-TX transmitter provides flexibility for applications
where data conversion is not always required. The
DP83848YB implements the 100BASE-TX transmit state
machine diagram as specified in the IEEE 802.3u Stan-
dard, Clause 24.
Figure 6. 100BASE-TX Transmit Block Diagram
4B5B CODE-
GROUP
ENCODER &
SCRAMBLER
NRZ TO NRZI
ENCODER
5B PARALLEL
TO SERIAL
PMD OUTPUT PAIR
TX_CLK
TXD[3:0] /
TX_EN
BINARY
TO MLT-3 /
COMMON
DRIVER
125MHZ CLOCK
BP_SCR
MUX
100BASE-TX
LOOPBACK
MLT[1:0]
DIVIDE
BY 5
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