參數(shù)資料
型號: DP83848YB/NOPB
廠商: National Semiconductor
文件頁數(shù): 62/86頁
文件大?。?/td> 0K
描述: IC TXRX ETHERNET PHYTERA 48-LQFP
標(biāo)準(zhǔn)包裝: 250
類型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: 以太網(wǎng)
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-LQFP 裸露焊盤(7x7)
包裝: 帶卷 (TR)
其它名稱: DP83848YBTR
www.national.com
64
D
P
83
848
YB
8.2 AC Specs
8.2.1 Power Up Timing
Parameter
Description
Notes
Min
Typ
Max
Units
T2.1.1
Post Power Up Stabilization
time prior to MDC preamble for
register accesses
MDIO is pulled high for 32-bit serial man-
agement initialization
X1 Clock must be stable for a min. of
167ms at power up.
167
ms
T2.1.2
Hardware Configuration Latch-
in Time from power up
Hardware Configuration Pins are de-
scribed in the Pin Description section
X1 Clock must be stable for a min. of
167ms at power up.
167
ms
T2.1.3
Hardware Configuration pins
transition to output drivers
50
ns
Vcc
Hardware
RESET_N
MDC
32 clocks
Latch-In of Hardware
Configuration Pins
Dual Function Pins
Become Enabled As Outputs
input
output
X1 clock
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