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參數(shù)資料
| 型號(hào)： | DS1023S-500+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 256TAP 16-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 標(biāo)片/步級(jí)數(shù)： | 256 |
| 功能： | 單發(fā)射，可編程 |
| 延遲到第一抽頭： | 16.5ns |
| 接頭增量： | 5ns |
| 可用的總延遲： | 1275ns |
| 獨(dú)立延遲數(shù)： | 1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 帶卷 (TR) |
DS1023
4 of 16
For highest accuracy it is strongly recommended that the reference delay is used. Variations in input
voltage levels and transition times can significantly alter the measured delay from input to output. This
effect is totally removed if the reference delay output is used. Furthermore, adverse effects on step zero
delay caused by process temperature coefficients are also cancelled out.
INPUT PULSE DURATION
The internal architecture of the DS1023 allows the output delay time to be considerably longer than the
input pulse width (see ac specifications). This feature is useful in many applications, in particular clock
phase control where delays up to and beyond one full clock period can be achieved.
MODE SELECT
The DS1023 has four possible output functions but only two output pins. The functionality of the two
output pins is determined by the Mode Select (MS) pin.
MS = 0 Figure 3
Output Function
Name
Pin Number
Reference Output
REF
9
Delayed Output
OUT
15
OUT is a copy of the input waveform that is delayed by an amount set by the programmed values (Table
1). A programmed value of zero will still result in a non-zero delay as indicated in the Step Zero delay
specification. The signal on OUT is the same polarity as the input.
REF is a fixed reference delay. It also is a copy of the input waveform but the delay interval is fixed to a
value approximately equal to the Step Zero Value of the device (as shown in the Reference Delay
specification). In fact the device is trimmed to ensure that the Reference Delay is always slightly longer
than the Step Zero Value (by 1.5 ns typically).
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