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參數(shù)資料
| 型號： | DS1023S-500+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 256TAP 16-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 標(biāo)片/步級數(shù)： | 256 |
| 功能： | 單發(fā)射，可編程 |
| 延遲到第一抽頭： | 16.5ns |
| 接頭增量： | 5ns |
| 可用的總延遲： | 1275ns |
| 獨(dú)立延遲數(shù)： | 1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 帶卷 (TR) |
DS1023
14 of 16
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the 1.5V
point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
D (Time Delay): The elapsed time between the 1.5V point on the edge of an input pulse and the 1.5V
point on the corresponding edge of the output pulse.
TIMING DIAGRAM: NON-LATCHED PARALLEL MODE
(P /S = 0, LE = 1) Figure 10
TIMING DIAGRAM: LATCHED PARALLEL MODE (P /S = 0) Figure 11
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| DS10-24B | 制造商:TRANSMISSION DEVELOPMENTS 功能描述:MOULDED SPUR GEAR 1.0, 24 |
| DS1027AS | 制造商:Maxim Integrated Products 功能描述:DS1027AS |
| DS102-K | 制造商:Miyama Electric 功能描述: |
| DS102-M | 制造商:Miyama Electric 功能描述: |
| DS102OS-50 | 制造商:Maxim Integrated Products 功能描述: |
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