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參數(shù)資料
| 型號： | DS1123LE-50+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 14/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 256TAP 16-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 標(biāo)片/步級數(shù)： | 256 |
| 功能： | 單發(fā)射，可編程 |
| 延遲到第一抽頭： | 16.5ns |
| 接頭增量： | 0.5ns |
| 可用的總延遲： | 127.5ns |
| 獨立延遲數(shù)： | 1 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 管件 |
DS1123L
3.3V, 8-Bit, Programmable Timing Element
_____________________________________________________________________
9
effect on power-up. The most flexibility when using par-
allel mode occurs when the delay is being controlled
by a microprocessor.
There are two common parallel interface implementa-
tions used to control the DS1123L using a microproces-
sor (see Figure 2). LE can be used to latch the data
from the microprocessor, which allows the data bus to
be shared with other peripherals, or LE can be tied
high, which causes the DS1123L to adjust its delay
immediately following a change to the parallel inputs.
For each configuration, a settling time (tEDV or tPDV) is
required after an adjustment is made before the input
signal is accurately delayed according to the new set-
ting. Figures 3 and 4 show the timing required for these
implementations.
Using the Serial Programming Interface
The 3-wire serial interface is enabled by connecting P/S
to VCC. Serial mode operates similar to a shift register.
When LE is set at a high logic level, it enables the reg-
ister and CLK clocks the data, D, into the register one
bit at a time starting with the most significant bit. After
all 8 bits are shifted into the DS1123L, LE is pulled low
to end the data transfer and activate the new value. A
settling time (tEDV) is required after LE is pulled low
before the signal delay meets its specified accuracy. A
timing diagram for the serial interface is shown in
Figure 6. The 3-wire interface also has an output (Q)
that can be used to cascade multiple 3-wire devices,
and it can be used to read the current value of the
devices on the bus.
LE
P0-P7
P/S
8
MICROPROCESSOR
ADDITIONAL
PERIPHERAL
ADDITIONAL
PERIPHERAL
A) SHARING THE PARALLEL INTERFACE
WITH ADDITIONAL PERIPHERALS
MICROPROCESSOR
8
B) A PARALLEL INTERFACE DEDICATED
TO A DS1123L
VCC
DS1123L
LE
P0-P7
P/S
DS1123L
Figure 2. Parallel Interface Options for DS1123L
PREVIOUS VALUE
PARALLEL
INPUTS
P0–P7
DELAY
TIME
NEW VALUE
PREVIOUS VALUE
tPDX
tPDV
Figure 3. Nonlatched Parallel Timing Diagram
ENABLE
(LE)
PREVIOUS VALUE
NEW VALUE
tEW
tDSE
tEDX
tEDV
tDHE
PARALLEL
INPUTS
PO–P7
DELAY
TIME
Figure 4. Latched Parallel Timing Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1123LE-50+ | 功能描述:延遲線/計時元素 Programmable 3.3V 8 Bit Timing Element RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS1123LS-200 | 功能描述:延遲線/計時元素 RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS1123LS-25 | 功能描述:延遲線/計時元素 RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS1123LS-50 | 功能描述:延遲線/計時元素 RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS1123S-100 | 功能描述:延遲線/計時元素 RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
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