參數(shù)資料
型號(hào): DS1123LE-50+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 2/14頁(yè)
文件大?。?/td> 0K
描述: IC DELAY LINE 256TAP 16-TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 96
標(biāo)片/步級(jí)數(shù): 256
功能: 單發(fā)射,可編程
延遲到第一抽頭: 16.5ns
接頭增量: 0.5ns
可用的總延遲: 127.5ns
獨(dú)立延遲數(shù): 1
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
DS1123L
3.3V, 8-Bit, Programmable Timing Element
10
_____________________________________________________________________
To read the current values stored by the 3-wire
device(s), the latch must be enabled and the value of Q
must be read and then written back to D before the
register is clocked. This causes the current value of the
register to be written back into the DS1123L as it is
being read. This can be accomplished in a couple of
different ways. If the microprocessor has an I/O pin that
is high impedance when set as an input, a feedback
resistor (generally between 1k
Ω and 10kΩ) can be
used to write the data on Q back to D as the value is
read (see Figure 5a). If the microprocessor has an
internal pullup on its I/O pins, or only offers separate
input and output pins, the value in the register can still
be read. The circuit shown in Figure 5b allows the Q
values to read by the microprocessor, which must write
the Q value to D before it can clock the bus to read the
next bit. If the Q values are read without writing them to
D (with the pullup or otherwise), the read is destructive.
A destructive read cycle likely results in an undesirable
change in the delay setting.
Figure 5c shows how to cascade multiple DS1123L’s
onto the same 3-wire bus. One important detail of writ-
ing software for cascaded 3-wire devices is that all the
devices on the bus must be written to or read from dur-
ing each read or write cycle. Attempting to write to only
the first device (U1) would cause the data stored in U1
MICROPROCESSOR
OUTPUT
I/O PIN
LE
CLK
DQ
RFB
MICROPROCESSOR
OUTPUT
INPUT
A) USING A FEEDBACK RESISTOR WITH AN I/O PIN FOR READING
THE DS1123L
B) USING A SEPARATE INPUT PIN TO READ THE DS1123L
MICROPROCESSOR
LE
CLK
DQ
LE
CLK
DQ
LE
CLK
DQ
OUTPUT
I/O PIN
RFB
C) CASCADING MULTIPLE DS1123L'S ON A 3-WIRE BUS
VCC
LE
CLK
DQ
P/S
DS1123L
U1
U2
U3
DS1123L
Figure 5. Using the Serial Interface
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參數(shù)描述
DS1123LE-50+ 功能描述:延遲線/計(jì)時(shí)元素 Programmable 3.3V 8 Bit Timing Element RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube
DS1123LS-200 功能描述:延遲線/計(jì)時(shí)元素 RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube
DS1123LS-25 功能描述:延遲線/計(jì)時(shí)元素 RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube
DS1123LS-50 功能描述:延遲線/計(jì)時(shí)元素 RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube
DS1123S-100 功能描述:延遲線/計(jì)時(shí)元素 RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube