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參數(shù)資料
| 型號： | DS1481S/T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BUS MASTER 1 WIRE 14-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 接口： | 1 線 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SOIC |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
DS1481
2 of 10
The DS1481’s 3V operation insures compatibility with most low power parallel ports (i.e., portable
computers).
DEVICE OPERATION
1-Wire communication is executed in “time slots”. The DS1481 generates either a read/write bit “time
slot” or a reset on the I/O pin. The operation performed is determined by the states of the D/CLK and
RES pins as follows:
TIME SLOT
D/CLK
RES
Toggle Speed
logic low
logic low (see Figure 7)
Read 0, Read 1, Write 1
logic high
logic high (see Figure 4)
Write 0
logic low
logic high (see Figure 5)
1-Wire Reset
logic high
logic low (see Figure 6)
After D/CLK and RES have been set, the time slot begins when ENI is driven to its active state. A falling
edge on ENI causes the DS1481 to save the state of D/CLK and RES. If the time slot is a 1-Wire reset the
DS1481 will issue a busy signal by driving O1/BSY1 low and O2/BSY2 high. After 2
μs O2/BSY2 is
driven low. Both outputs will remain low until the communication on the I/O line is finished. A busy
signal for a bit time slot differs from the reset busy signal only in that both O1/BSY1 and O2/BSY2 are
driven low immediately.
While the busy signal is asserted, the host processor is free to perform other tasks (including running the
print spooler). When the time slot is complete, the DS1481 restores both O1/BSY1 and O2/BSY2 to the
states of I1 and I2 (see Figure 1).
When the host detects that one or both of the busy signals has returned high, it must query the result of
the time slot. This is accomplished by driving D/CLK low. If the result of the time slot was low (Read 0,
Write 0 or presence detect) the DS1481 drives both O1/BSY1 and O2/BSY2 low (this state is held until
ENI returns high). Otherwise it propagates the states of I1 and I2.
After the host reads the result of the time slot it must drive ENI to its inactive state (high). The DS1481
will then set O1/BSY1 and O2/BSY2 to the states of I1 and
1-WIRE TIMING GENERATION
For all time slots, the DS1481 samples the I/O pin at tSO (see Figure 4). The DS1481 waits a minimun of
60
μs from the start of the time slot and de-asserts O1/BSY1 and O2/BSY2.
When a reset is requested, the DS1481 drives the I/O pin low for at least 480
μs and then releases it.
During a normal reset the I/O pin immediately begins to return high.
If a 1-Wire device is present on the I/O line it pulls I/O low after time T (15
μs ≤ T ≤ 60μs) from the
previous rising edge. The 1-Wire device(s) holds the I/O line low for 4T and then releases it, allowing the
I/O line to return high. This is the presence detect pulse. The I/O line must remain high (in its idle state)
for at least 3T before the 1-Wire device(s) is ready for further communication. To ensure this idle high
time is satisfied, the DS1481 does not release O1/BSY1 and O2/BSY2 for at least 960
μs (measured from
the 1st falling edge on the I/O pin).
Not
Recommended
for
New
Design
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| DS1482 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:1-Wire Level Shifter and Line Driver with Load Sensor |
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