tSIO <" />
參數(shù)資料
型號: DS1481S/T&R
廠商: Maxim Integrated Products
文件頁數(shù): 7/10頁
文件大?。?/td> 0K
描述: IC BUS MASTER 1 WIRE 14-SOIC
標(biāo)準(zhǔn)包裝: 2,500
接口: 1 線
電源電壓: 2.7 V ~ 5.5 V
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 14-SOIC
包裝: 帶卷 (TR)
安裝類型: 表面貼裝
DS1481
6 of 10
Figure 4. TIMING DIAGRAM: HOST INTERFACE
Figure 5. TIMING DIAGRAM: HOST INTERFACE
tSIO = 8 μs (STANDARD SPEED), tBLB = 60 μs (MINIMUM)
tSIO = 2 μs (OVERDRIVE SPEED), tBLB = 6 μs (MINIMUM)
READ O, READ 1, WRITE 1 BIT TIME SLOTS
ENI
VALID
RES
VALID
O1/BSY1
O2/BSY2
tBLB
READ 0
(I/O)
READ 1
(I/O)
WRITE 1
(I/O)
tSIO
ENI
D/CLK
VALID
RES
VALID
O1/BSY1
O2/BSY2
WRITE 0
(I/O)
tBLB = 60 μs (MINIMUM)
tBLB = 6 μs (MINIMUM)
(OD = 0)
(OD = 1)
WRITE 0 TIME SLOT
tBLB
D/CLK
(OD = 0)
(OD = 1)
Not
Recommended
for
New
Design
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