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參數(shù)資料
| 型號： | DS1481S/T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BUS MASTER 1 WIRE 14-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 接口： | 1 線 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SOIC |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
DS1481
4 of 10
EPP/ECP TRANSPARENT MODE
When the DS1481 first powers up it is in a transparent mode in which the three signal lines (auto line
feed, busy and select) that pass through the part are directly connected by transmission gates. This allows
bi-directional printers (or other parallel port peripherals) to communicate in either the EPP or ECP mode
of the PC parallel port. The DS1481 pin sets connected are as follows:
ENI
ENO
O1/BSY1
I1
O2/BSY2
I2
1-Wire communication using the DS1481 is impossible in transparent mode. To toggle to normal mode
four consecutive overdrive toggle commands must be issued. If this sequence has been issued and the
ENI pin remains high for at least 10ms the part will enter its normal mode of operation. Note that any
other 1-Wire time slot command issued during the sequence resets the sequence. The steps needed to
return to transparent mode are as described above with the exception that no additional wait is required at
the end of the four overdrive toggles to enter transparent mode.
While in transparent mode if the DS1481 detects that the ENO pin has been held low for more than 10ms
it turns off the transmission gate connecting ENI and ENO. This guarantees the host will have the ability
to take the DS1481 out of transparent mode and perform 1-Wire I/O operations.
Figure 1. DS1481 FUNCTIONAL BLOCK DIAGRAM
50K
I2
I1
O1/BSY1
O2/BSY2
I/O
RES
ENI
D/CLK
ENO
LAST PART
DETECTION
1-WIRE BUS
MASTER
OD
D
Q
CLK
Q
D
Q
CLK
Q
Not
Recommended
for
New
Design
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