DS1884
SFP and PON ONU Controller
with Digital LDD Interface
13
Maxim Integrated
I2C AC ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +3.6V, TA = -40NC to +95NC, unless otherwise noted. Timing is referenced to VIL(MAX) and VIH(MIN).) (See Figure 18.) NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.85V to +3.6V, unless otherwise noted.)
Note 1: All voltages are referenced to ground. Current entering the IC is considered positive, and current exiting the IC is consid-
ered negative.
Note 2: Inputs are at supply rail. Outputs are not loaded. Does not include REFIN current. Measured using the
Typical OperatingNote 3: The ADC output is available internally as a 16-bit value. The 16 bits are derived by left-shifting the 13-bit ADC output by 3.
Note 4: Guaranteed by design.
Note 5: TXB (transmit bias) and TXP (transmit power) are separate ADC conversions that are performed on the same input pin,
TXMON.
Note 6: Full scale is user-programmable.
Note 7: Time until faults are cleared (falling edge of TXFOUT).
Note 8: Time until rising edge of TXDOUT.
Note 9: Time until falling edge of TXDOUT.
Note 10: Time until completion of initial MAX3710 control registers configuration.
Note 11: Time until completion of initial MAX3945 and MAX3710 control registers configuration.
Note 12: VCC LO alarm or warning is enabled, a VCC conversion is completed, and VCC is above VCC LO alarm or warning. See
Note 13: DAC output valid, 3-wire writes from LUTs complete, and digital outputs valid.
Note 14: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C stan-
dard mode.
Note 15: CB = Total capacitance of one bus line in pF.
Note 16: EEPROM write begins after a STOP condition occurs.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
fSCL
(Note 14)
0
400
kHz
Clock Pulse-Width Low
tLOW
1.3
F
s
Clock Pulse-Width High
tHIGH
0.6
F
s
Bus Free Time Between STOP and
START Condition
tBUF
1.3
F
s
START Hold Time
tHD:STA
0.6
F
s
START Setup Time
tSU:STA
0.6
F
s
Data in Hold Time
tHD:DAT
0
0.9
F
s
Data in Setup Time
tSU:DAT
100
ns
Rise Time of Both SDA and SCL
Signals
tR
(Note 15)
20 +
0.1CB
300
ns
Fall Time of Both SDA and SCL
Signals
tF
(Note 15)
20 +
0.1CB
300
ns
STOP Setup Time
tSU:STO
0.6
F
s
Capacitive Load for Each Bus Line
CB
400
pF
EEPROM Write Time
tW
(Note 16)
20
ms
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EEPROM Write Cycles
At TA = +25NC
50,000
—
At TA = +85NC
10,000