參數(shù)資料
型號(hào)： DS21354LC1+
廠商： Maxim Integrated Products
文件頁數(shù)： 97/124頁
文件大?。?/td> 0K
描述： IC TXRX E1 3.3V 100-LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 90
功能： 單芯片收發(fā)器
接口： E1，HDLC
電路數(shù)： 1
電源電壓： 3.14 V ~ 3.47 V
電流 - 電源： 75mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤
包括： 遠(yuǎn)程和 AIS 警報(bào)檢測器 / 發(fā)生器
產(chǎn)品目錄頁面： 1430 (CN2011-ZH PDF)
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
74 of 124
HSR: HDLC STATUS REGISTER (Address = B1 Hex)
(MSB)
(LSB)
FRCL
RPE
RPS
RHALF
RNE
THALF
TNF
TMEND
SYMBOL
POSITION
NAME AND DESCRIPTION
FRCL
HSR.7
Framer Receive Carrier Loss. Set when 255 (or 2048 if CCR3.0 = 1)
consecutive zeros have been detected at RPOSI and RNEGI.
RPE
HSR.6
Receive Packet End. Set when the HDLC controller detects either the
finish of a valid message (i.e., CRC check complete) or when the
controller has experienced a message fault such as a CRC checking error,
or an overrun condition, or an abort has been seen. The setting of this bit
prompts the user to read the RHIR register for details.
RPS
HSR.5
Receive Packet Start. Set when the HDLC controller detects an opening
byte. The setting of this bit prompts the user to read the RHIR register for
details.
RHALF
HSR.4
Receive FIFO Half Full. Set when the receive 64-byte FIFO fills beyond
the halfway point. The setting of this bit prompts the user to read the
RHIR register for details.
RNE
HSR.3
Receive FIFO Not Empty. Set when the receive 64-byte FIFO has at
least one byte available for a read. The setting of this bit prompts the user
to read the RHIR register for details.
THALF
HSR.2
Transmit FIFO Half Empty. Set when the transmit 64-byte FIFO
empties beyond the halfway point. The setting of this bit prompts the user
to read the THIR register for details.
TNF
HSR.1
Transmit FIFO Not Full. Set when the transmit 64-byte FIFO has at
least one byte available. The setting of this bit prompts the user to read the
THIR register for details.
TMEND
HSR.0
Transmit Message End. Set when the transmit HDLC controller has
finished sending a message. The setting of this bit prompts the user to read
the THIR register for details.
Note: The RPE, RPS, and TMEND bits are latched and are cleared when read.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21354LC1+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3/5V E1 Single Chip Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21354LN 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3/5V E1 Single Chip Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21354LN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3/5V E1 Single Chip Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21372 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V Bit Error Rate Tester BERT
DS21372T 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V Bit Error Rate Tester (BERT) RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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