參數(shù)資料
型號: DS21354LN
廠商: Maxim Integrated Products
文件頁數(shù): 55/124頁
文件大?。?/td> 0K
描述: IC TXRX E1 1-CHIP 3.3V 100-LQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
產(chǎn)品變化通告: Product Discontinuation 20/Feb/2012
標準包裝: 90
功能: 單芯片收發(fā)器
接口: E1,HDLC
電路數(shù): 1
電源電壓: 3.14 V ~ 3.47 V
電流 - 電源: 75mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設備封裝: 100-LQFP(14x14)
包裝: 托盤
包括: 遠程和 AIS 警報檢測器 / 發(fā)生器
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
36 of 124
CCR1: COMMON CONTROL REGISTER 1 (Address = 14 Hex)
(MSB)
(LSB)
FLB
THDB3
TG802
TCRC4
RSM
RHDB3
RG802
RCRC4
SYMBOL
POSITION
NAME AND DESCRIPTION
FLB
CCR1.7
Framer Loopback.
0 = loopback disabled
1 = loopback enabled
THDB3
CCR1.6
Transmit HDB3 Enable.
0 = HDB3 disabled
1 = HDB3 enabled
TG802
CCR1.5
Transmit G.802 Enable. See Section 18 for details.
0 = do not force TCHBLK high during bit 1 of time slot 26
1 = force TCHBLK high during bit 1 of time slot 26
TCRC4
CCR1.4
Transmit CRC4 Enable.
0 = CRC4 disabled
1 = CRC4 enabled
RSM
CCR1.3
Receive Signaling Mode Select.
0 = CAS signaling mode
1 = CCS signaling mode
RHDB3
CCR1.2
Receive HDB3 Enable.
0 = HDB3 disabled
1 = HDB3 enabled
RG802
CCR1.1
Receive G.802 Enable. See Section 18 for details.
0 = do not force RCHBLK high during bit 1 of time slot 26
1=force RCHBLK high during bit 1 of time slot 26
RCRC4
CCR1.0
Receive CRC4 Enable.
0 = CRC4 disabled
1 = CRC4 enabled
5.3.
Framer Loopback
When CCR1.7 is set to one, the DS21354/DS21554 enter a framer loopback (FLB) mode. See Figure 2-1
for more details. This loopback is useful in testing and debugging applications. In FLB, the SCT will loop
data from the transmit side back to the receive side. When FLB is enabled, the following will occur:
1) Data will be transmitted as normal at TPOSO and TNEGO.
2) Data input via RPOSI and RNEGI will be ignored.
3) The RCLK output will be replaced with the TCLK input.
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