參數(shù)資料
型號: DS2143QN/T&R
廠商: Maxim Integrated Products
文件頁數(shù): 11/44頁
文件大小: 0K
描述: IC CONTROLLER E1 5V LP 44-PLCC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 500
控制器類型: E1 控制器
接口: 并行/串行
電源電壓: 4.5 V ~ 5.5 V
電流 - 電源: 10mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 帶卷 (TR)
DS2143/DS2143Q
19 of 44
SR2: STATUS REGISTER 2 (Address=07 Hex)
(MSB)
(LSB)
RMF
RAF
TMF
SEC
TAF
LOTC
RCMF
LORC
SYMBOL
POSITION
NAME AND DESCRIPTION
RMF
SR2.7
Receive CAS Multiframe. Set every 2 ms (regardless if CAS
signaling is enabled or not) on receive multiframe boundaries.
Used to alert the host that signaling data is available.
RAF
SR2.6
Receive Align Frame. Set every 250
s at the beginning of
align frames. Used to alert the host that Si and Sa bits are
available in the RAF and RNAF registers.
TMF
SR2.5
Transmit Multiframe. Set every 2 ms (regardless if CRC4 is
enabled) on transmit multiframe boundaries. Used to alert the
host that signaling data needs to be updated.
SEC
SR2.4
One-Second Timer. Set on increments of 1 second based on
RCLK.
TAF
SR2.3
Transmit Align Frame. Set every 250
s at the beginning of
align frames. Used to alert the host that the TAF and TNAF
registers need to be updated.
LOTC
SR2.2
Loss of Transmit Clock. Set when the TCLK pin has not
transitioned for one channel time (or 3.9
s). Will force pin 34
high if enabled via TCR2.0. Based on RCLK.
RCMF
SR2.1
Receive
CRC4
Multiframe.
Set
on
CRC4
multiframe
boundaries; will continue to be set every 2 ms on an arbitrary
boundary if CRC4 is disabled.
LORC
SR2.0
Loss of Receive Clock. Set when the RCLK pin has not
transitioned for at least 2
s (3 s ±1 s).
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