參數(shù)資料
型號： DS2143QN/T&R
廠商： Maxim Integrated Products
文件頁數(shù)： 14/44頁
文件大?。?/td> 0K
描述： IC CONTROLLER E1 5V LP 44-PLCC
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 500
控制器類型： E1 控制器
接口： 并行/串行
電源電壓： 4.5 V ~ 5.5 V
電流 - 電源： 10mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應商設備封裝： 44-PLCC（16.59x16.59）
包裝： 帶卷 (TR)
DS2143/DS2143Q
21 of 44
IMR2: INTERRUPT MASK REGISTER 2 (Address=17 Hex)
(MSB)
(LSB)
RMF
RAF
TMF
SEC
TAF
LOTC
RCMF
LORC
SYMBOL
POSITION
NAME AND DESCRIPTION
RMF
IMR2.7
Receive CAS Multiframe.
0 = interrupt masked.
1 = interrupt enabled.
RAF
IMR2.6
Receive Align Frame.
0 = interrupt masked.
1 = interrupt enabled.
TMF
IMR2.5
Transmit Multiframe.
0 = interrupt masked.
1 = interrupt enabled.
SEC
IMR2.4
1-Second Timer.
0 = interrupt masked.
1 = interrupt enabled.
TAF
IMR2.3
Transmit Align Frame.
0 = interrupt masked.
1 = interrupt enabled.
LOTC
IMR2.2
Loss Of Transmit Clock.
0 = interrupt masked.
1 = interrupt enabled.
RCMF
IMR2.1
Receive CRC4 Multiframe.
0 = interrupt masked.
1 = interrupt enabled.
LORC
IMR2.0
Loss of Receive Clock.
0 = interrupt masked.
1 = interrupt enabled.
5.0 ERROR COUNT REGISTERS
There are a set of three counters in the DS2143 that record bipolar violations, errors in the CRC4 SMF
code words, and E-bits as reported by the far end. Each of these three counters are automatically updated
on 1-second boundaries as determined by the 1-second timer in Status Register 2 (SR2.4). Hence, these
registers contain performance data from the previous second. The user can use the interrupt from the 1-
second timer to determine when to read these registers. The user has a full second to read the counters
before the data is lost.
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