參數(shù)資料
型號(hào): DS2151QN
廠商: Maxim Integrated Products
文件頁數(shù): 14/60頁
文件大?。?/td> 0K
描述: IC TXRX T1 1-CH 5V LP IND 44PLCC
標(biāo)準(zhǔn)包裝: 1
功能: 單芯片收發(fā)器
接口: T1
電路數(shù): 1
電源電壓: 4.75 V ~ 5.25 V
電流 - 電源: 65mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 管件
包括: 警報(bào)檢測器和發(fā)生器,CSU 回路代碼發(fā)生器和檢測器,DSX-1和CSU 線路補(bǔ)償發(fā)生器
DS2151Q
21 of 60
RIR2: RECEIVE INFORMATION REGISTER 2 (Address = 31 Hex)
(MSB)
(LSB)
RL1
RL0
TESF
TESE
TSLIP
JALT
RPDV
TPDV
SYMBOL
POSITION
NAME AND DESCRIPTION
RL1
RIR2.7
Receive Level Bit 1. See Table 5-1.
RL0
RIR2.6
Receive Level Bit 0. See Table 5-1.
TESF
RIR2.5
Transmit Elastic Store Full. Set when the transmit elastic
store buffer fills and a frame is deleted.
TESE
RIR2.4
Transmit Elastic Store Empty. Set when the transmit elastic
store buffer empties and a frame is repeated.
TSLIP
RIR2.3
Transmit Elastic Store Slip Occurrence. Set when the
transmit elastic store has either repeated or deleted a frame.
JALT
RIR2.2
Jitter Attenuator Limit Trip. Set when the jitter attenuator
FIFO reaches to within 4 bits of its limit; useful for debugging
jitter attenuation operation.
RPDV
RIR2.1
Receive Pulse Density Violation. Set when the receive data
stream does not meet the ANSI T1.403 requirements for pulse
density.
TPDV
RIR2.0
Transmit Pulse Density Violation. Set when the transmit data
stream does not meet the ANSI T1.403 requirements for pulse
density.
Table 5-1. Receive T1 Level Indication
RL1
RL0
TYPICAL LEVEL
RECEIVED (dB)
0
+2 to -7.5
0
1
-7.5 to -15
1
0
-15 to -22.5
1
Less than -22.5
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